Texas Instruments TMS320C3x 사용자 설명서

 Parallel MPYI3 and ADDI3

13-165

  Assembly Language Instructions

31

24 23

16

8 7

0

15

1 0

0 0 1 0

P

src

4

src

3

src

1

src

2

d1 d2

An integer multiplication and an integer addition are performed in parallel. All
registers are read at the beginning and loaded at the end of the execute cycle.
This means that if one of the parallel operations (MPYI3) reads from a register
and the operation being performed in parallel (ADDI3) writes to the same reg-
ister, MPYI3 accepts the contents of the register as input before it is modified
by the ADDI3.

Any combination of addressing modes can be coded for the four possible
source operands as long as two are coded as indirect and two are coded as
register. The assignment of the source operands 

srcA – srcD to the

src1 – src4 fields varies, depending on the combination of addressing modes
used, and the P field is encoded accordingly. To simplify processing when the
order is not significant, the assembler may change the order of operands in
commutative operations.

1 (see 

Note: Cycle Count on page 13–167)

These condition flags are modified only if the destination register is R7 – R0.

Unaffected

1 if an integer overflow occurs; unchanged otherwise

0

0

0

1 if an integer overflow occurs; 0 otherwise

Unaffected

Operation is affected by OVM bit value.

MPYI3 R7,R4,R0

||

ADDI3 *–AR3,*AR5

– –

(1),R3