Texas Instruments TMS320C3x 사용자 설명서

 Parallel MPYI3 and STI

13-167

  Assembly Language Instructions

src2, src1, dst1

||

STI 

src3, dst2

src1 

×

 src2 

→

 dst1

||

src3 

→

 dst2

src1

register (R

n1, 0 

≤

 

n1 

≤

 7)

src2

indirect (

disp = 0, 1, IR0, IR1)

dst1

register (R

n3, 0 

≤

 

n3 

≤

 7)

src3

register (R

n4, 0 

≤

 

n4 

≤

 7)

dst2

indirect (

disp = 0, 1, IR0, IR1)

This instruction’s operands have been augmented in the following devices:

-

’C31 silicon revision 6.0 or greater

-

’C32 silicon revision 2.0 or greater

src1

register (R

n1, 0 

≤

 

n1 

≤

 7)

src2

indirect (

disp = 0, 1, IR0, IR1) or any CPU register

dst1

register (R

n2, 0 

≤

 

n2 

≤

 7)

src3

register (R

n3, 0 

≤

 

n3 

≤

 7)

dst2

indirect (

disp = 0, 1, IR0, IR1)

31

24 23

16

8 7

0

15

1 1

1 0 0 0

dst

1

src

2

dst

2

0

src

1

src

3

An integer multiplication and an integer store are performed in parallel. All reg-
isters are read at the beginning and loaded at the end of the execute cycle. If
one of the parallel operations (STI) reads from a register and the operation be-
ing performed in parallel (MPYI3) writes to the same register, STI accepts as
input the contents of the register before it is modified by the MPYI3.

If 

src2 and dst2 point to the same location, src2 is read before the write to dst2.

Integer overflow occurs when any of the 16 MSBs of the 48-bit result differ from
the MSB of the 32-bit output value.

1