Texas Instruments TMS320C3x 사용자 설명서
MPYI3||STI
Parallel MPYl3 and STI
13-168
Status Bits
These condition flags are modified only if the destination register is R7 – R0.
LUF
Unaffected
LV
1 if an integer overflow occurs; unchanged otherwise
UF
0
N
1 if a negative result is generated; 0 otherwise
Z
1 if a 0 result is generated; 0 otherwise
V
1 if an integer overflow occurs; 0 otherwise
C
Unaffected
OVM
Operation is affected by OVM bit value.
Example
MPYI3
*++AR0(1),R5,R7
||
STI
R2,*–AR3(1)
Before Instruction
After Instruction
R2
00 0000 00DC
R2
00 0000 00DC
R5
00 0000 0032
R5
00 0000 0032
R7
00 0000 0000
R7
00 0000 2710
AR0
80 995A
AR0
80 995B
AR3
80 982F
AR3
80 982F
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
80995Bh
0C8
80995Bh
0C8
80982Eh
0
80982Eh
ODC
220
220
200
10000
50
50
220
200
Note:
Cycle Count
See Section 8.5.2,
Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
Mode Bit