Texas Instruments TMS320TCI648x 사용자 설명서
www.ti.com
Source Address
DMA Read
Destination Address
Count
Byte Count
DSP Address
RSV
Interrupt Req
0
0
1
7
23
8
DestID
25
24
ID Size
27
26
xambs
29
28
Priority
OutPortID
31
30
Hop Count
Drbll
31
16 15
Packet
8
7
0
RapioIO Address/Config_offset
NodeID
CRC
16
Count*8
payload
2
xamsbs
1
wr ptr
29
address
32
ext addr
8
srcTID
4
wrsize
4
trans
8
sourceID
8
destID
4
ftype
2
tt
2
prio
3
rsv
5
ackID
TX Shared Buffer Pool
rdsize/
wsize
rdptr/
wptr
Count
translator
LSU _REG4
n
LSU _REG2
n
LSU _REG3
n
LSU _REG0
LSU _REG1
LSU _REG1
n
n
n
LSU _REG5
n
2.3.3.1
Detailed Data Path Description
SRIO Functional Description
Figure 14. Example Burst NWRITE_R
For WRITE commands, the payload is combined with the header information from the control/command
registers and buffered in the shared TX buffer resource pool. Finally, it is forwarded to the TX FIFO for
transmission. READ commands have no payload. In this case, only the control/command register fields
are buffered and used to create a RapidIO NREAD packet, which is forwarded to the TX FIFO.
Corresponding response packet payloads from READ transactions are buffered in the shared RX buffer
resource pool when forwarded from the receive ports. Both posted and non-posted operations rely on the
OutPortID command register field to specify the appropriate output port/FIFO.
registers and buffered in the shared TX buffer resource pool. Finally, it is forwarded to the TX FIFO for
transmission. READ commands have no payload. In this case, only the control/command register fields
are buffered and used to create a RapidIO NREAD packet, which is forwarded to the TX FIFO.
Corresponding response packet payloads from READ transactions are buffered in the shared RX buffer
resource pool when forwarded from the receive ports. Both posted and non-posted operations rely on the
OutPortID command register field to specify the appropriate output port/FIFO.
The data is burst internally to the Load/Store module at the DMA clock rate.
The Load/Store module is for generating all outgoing RapidIO direct I/O packets. Any read or write
transaction, other than the messaging protocol, uses this interface. In addition, outgoing DOORBELL
packets are generated through this interface.
transaction, other than the messaging protocol, uses this interface. In addition, outgoing DOORBELL
packets are generated through this interface.
The data path for this module uses DMA bus as the DMA interface. The configuration bus is used by the
CPU to access the control/command registers. The registers contain transfer descriptors that are needed
to initiate READ and WRITE packet generation. After the transfer descriptors are written, flow control
status is queried. The unit examines the DESTID and PRIORITY fields of LSUn_REG4 to determine if that
flow has been Xoffd. Additionally, the free buffer status of the TX FIFO is checked (based on the
OutPortID register field). Only after the flow control access is granted, and a TX FIFO buffer has been
allocated, can a DMA bus read command be issued for payload data to be moved into the shared TX
buffer. Data is moved from the shared TX buffer to the appropriate output TX FIFO in simple sequential
order based on completion of the DMA bus transaction. However, if fabric congestion occurs, priority can
affect the order in which the data leaves the TX FIFOs.
CPU to access the control/command registers. The registers contain transfer descriptors that are needed
to initiate READ and WRITE packet generation. After the transfer descriptors are written, flow control
status is queried. The unit examines the DESTID and PRIORITY fields of LSUn_REG4 to determine if that
flow has been Xoffd. Additionally, the free buffer status of the TX FIFO is checked (based on the
OutPortID register field). Only after the flow control access is granted, and a TX FIFO buffer has been
allocated, can a DMA bus read command be issued for payload data to be moved into the shared TX
buffer. Data is moved from the shared TX buffer to the appropriate output TX FIFO in simple sequential
order based on completion of the DMA bus transaction. However, if fabric congestion occurs, priority can
affect the order in which the data leaves the TX FIFOs.
Here a reordering mechanism exists, which transmits the highest priority packets first if RETRY
acknowledges. Once in the FIFO, the data is guaranteed to be transmitted through the pins. Alternatively,
if an intended flow has been shut down, the peripheral signals the CPU with an interrupt to notify that the
packet was not sent and sets the completion code to 010b in the status register. The registers are held
until the interrupt service routine is complete before the BSY signal is released (BSY=0 in LSUn_REG6)
and the CPU can then rewrite or overwrite the transfer descriptors with new data.
acknowledges. Once in the FIFO, the data is guaranteed to be transmitted through the pins. Alternatively,
if an intended flow has been shut down, the peripheral signals the CPU with an interrupt to notify that the
packet was not sent and sets the completion code to 010b in the status register. The registers are held
until the interrupt service routine is complete before the BSY signal is released (BSY=0 in LSUn_REG6)
and the CPU can then rewrite or overwrite the transfer descriptors with new data.
illustrates the
data path and buffering that is required to support the Load/Store module.
SPRUE13A – September 2006
Serial RapidIO (SRIO)
39