Motorola MCF5281 사용자 설명서

7-2

MOTOROLA

 

The following subsection describes the PMM registers.

Implementation of low-power stop mode and exit from a low-power mode via an interrupt
require communication between the CPU and logic associated with the interrupt controller.
The LPICR is an 8-bit register that enables entry into low-power stop mode, and includes
the setting of the interrupt level needed to exit a low-power mode. 

The setting of the low-power mode select (LPMD) field in the
power management module’s low-power control register
(LPCR) determines which low-power mode the device enters
when a STOP instruction is issued.

If this field is set to enter stop mode, then the ENBSTOP bit in
the LPICR must also be set.

Following is the sequence of operations needed to enable this functionality:

1. The LPICR is programmed, setting the ENBSTOP bit (if stop mode is the desired 

low-power mode) and loading the appropriate interrupt priority level.

2. At the appropriate time, the processor executes the privileged STOP instruction. 

Once the processor has stopped execution, it asserts a specific Processor Status 
(PST) encoding. Issuing the STOP instruction when the LPICR[ENBSTOP] bit is 
set causes the SCM to enter stop mode.

1

S = CPU supervisor mode access only. User mode accesses to supervisor only addresses have no effect and result in a cycle 
termination transfer error.

0x0000_0010

Core Reset Status 

Register (CRSR)

 2

2

The CRSR, CWCR, and CWSR are described in the System Integration Module. They are shown here only to warn against 
accidental writes to these registers when accessing the LPICR.

Core Watchdog 

Control Register 

(CWCR)

Low-Power Interrupt 

Control Register 

(LPICR)

Core Watchdog 

Service Register 

(CWSR)

S

0x0011_0004

Chip Configuration Register (CCR)

 3

3

The CCR is described in the Chip Configuration Module. It is shown here only to warn against accidental writes to this register when 
accessing the LPCR.

Reserved

Low-Power Control 

Register (LPCR)

S