Motorola MCF5281 사용자 설명서

MOTOROLA

Chapter 7.  Power Management  

7-3

3. The entry into a low-power mode is processed by the low-power mode control 

logic, and the appropriate clocks (usually those related to the high-speed processor 
core) are disabled.

4. After entering the low-power mode, the interrupt controller enables a 

combinational logic path which evaluates any unmasked interrupt requests. The 
device waits for an event to generate an interrupt request with a priority level 
greater than the value programmed in LPICR[XLPM_IPL[2:0]].

Only fixed (external) interrupt can bring a device out of stop
mode. To exit from other low-power modes, such as doze or
wait, either fixed or programmable interrupts may be used;
however, the module generating the interrupt must be enabled
in that particular low-power mode. 

5. Once an appropriately-high interrupt request level arrives, the interrupt controller 

signals its presence, and the SIM responds by asserting the request to exit 
low-power mode.

6. The low-power mode control logic senses the request signal and re-enables the 

appropriate clocks.

7. With the processor clocks enabled, the core processes the pending interrupt request.

7

6

4

3

0

Field ENBSTOP

XLPM_IPL[2:0]

—

Reset

1/0

0

1/0

0

Undefined

R/W

R/W

Address

IPSBAR + 0x012

7

ENBSTOP

Enable low-power stop mode.
0 Low-power stop mode disabled
1 Low-power stop mode enabled. Once the core is stopped and the signal to enter stop mode is 

asserted, processor clocks can be disabled.

6–4

XLPM_IPL[2:0] Exit low-power mode interrupt priority level. This field defines the interrupt priority level needed to 

exit the low-power mode.Refer to Table 7-3.

3–0

—

Reserved, should be cleared.