Motorola MCF5281 사용자 설명서

MOTOROLA

Chapter 12.  Chip Select Module  

12-1

This chapter describes the MCF5282 chip select module, including the operation and
programming model of the chip select registers, which include the chip select address,
mask, and control registers.

Unless otherwise noted, in this chapter, “clock” refers to the
CLKOUT used for the bus.

The following list summarizes the key chip select features:

• Up to seven independent, user-programmable chip select signals (CS[6:0]) that can 

interface with external SRAM, PROM, EPROM, EEPROM, Flash, and peripherals

• Address masking for 64-Kbyte to 4-Gbyte memory block sizes 

Table 12-1 lists signals used by the chip select module.

Chip Selects 
(CS[6:0])

Each CSn can be independently programmed for an address location as well as for masking, port 
size, read/write burst capability, wait-state generation, and internal/external termination. Only CS0 is 
initialized at reset and may act as an external boot chip select to allow boot ROM to be at an external 
address space. Port size for CS0 is configured by the logic levels of D[19:18] when RSTO negates 
and RCON is asserted.

Output Enable 
(OE)

Interfaces to memory or to peripheral devices and enables a read transfer. It is asserted and negated 
on the falling edge of the clock. OE is asserted only when one of the chip selects matches for the 
current address decode.

Byte Strobes 
BS[3:0]

These signals are individually programmed through the byte-enable mode bit, CSCRn[BEM], 
described in Section 12.4.1.3.
These generated signals provide byte data select signals, which are decoded from the transfer size, 
A1, and A0 signals in addition to the programmed port size and burstability of the memory accessed, 
as Table 12-2 shows.