Motorola MCF5281 사용자 설명서
MOTOROLA
Chapter 29. Debug Support
29-37
Real-Time Debug Support
Operand Data:
Longword data is written into the specified debug register. The data
is supplied most-significant word first.
is supplied most-significant word first.
Result Data:
Command complete status (0xFFFF) is returned when register write
is complete.
is complete.
29.6 Real-Time Debug Support
The ColdFire Family provides support debugging real-time applications. For these types of
embedded systems, the processor must continue to operate during debug. The foundation
of this area of debug support is that while the processor cannot be halted to allow
debugging, the system can generally tolerate small intrusions into the real-time operation.
embedded systems, the processor must continue to operate during debug. The foundation
of this area of debug support is that while the processor cannot be halted to allow
debugging, the system can generally tolerate small intrusions into the real-time operation.
The debug module provides three types of breakpoints—PC with mask, operand address
range, and data with mask. These breakpoints can be configured into one- or two-level
triggers with the exact trigger response also programmable. The debug module
programming model can be written from either the external development system using the
debug serial interface or from the processor’s supervisor programming model using the
WDEBUG instruction. Only CSR is readable using the external development system.
range, and data with mask. These breakpoints can be configured into one- or two-level
triggers with the exact trigger response also programmable. The debug module
programming model can be written from either the external development system using the
debug serial interface or from the processor’s supervisor programming model using the
WDEBUG instruction. Only CSR is readable using the external development system.
29.6.1 Theory of Operation
Breakpoint hardware can be configured to respond to triggers in several ways. The response
desired is programmed into TDR. As shown in Table 29-21, when a breakpoint is triggered,
an indication (CSR[BSTAT]) is provided on the DDATA output port when it is not
displaying captured processor status, operands, or branch addresses.
desired is programmed into TDR. As shown in Table 29-21, when a breakpoint is triggered,
an indication (CSR[BSTAT]) is provided on the DDATA output port when it is not
displaying captured processor status, operands, or branch addresses.
The breakpoint status is also posted in the CSR. Note that CSR[BSTAT] is cleared by a CSR
read when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and a
level-2 breakpoint is not enabled. Status is also cleared by writing to TDR.
BDM instructions use the appropriate registers to load and configure breakpoints. As the
system operates, a breakpoint trigger generates the response defined in TDR.
read when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and a
level-2 breakpoint is not enabled. Status is also cleared by writing to TDR.
BDM instructions use the appropriate registers to load and configure breakpoints. As the
system operates, a breakpoint trigger generates the response defined in TDR.
PC breakpoints are treated in a precise manner—exception recognition and processing are
initiated before the excepting instruction is executed. All other breakpoint events are
initiated before the excepting instruction is executed. All other breakpoint events are
Table 29-21. DDATA[3:0]/CSR[BSTAT] Breakpoint Response
DDATA[3:0]/CSR[BSTAT]
1
1
Encodings not shown are reserved for future use.
Breakpoint Status
0000/0000
No breakpoints enabled
0010/0001
Waiting for level-1 breakpoint
0100/0010
Level-1 breakpoint triggered
1010/0101
Waiting for level-2 breakpoint
1100/0110
Level-2 breakpoint triggered