Motorola MCF5281 사용자 설명서
MOTOROLA
Chapter 29. Debug Support
29-39
Real-Time Debug Support
• Setting CSR[TRC] forces the processor into emulation mode when trace exception
processing begins.
While operating in emulation mode, the processor exhibits the following properties:
• All interrupts are ignored, including level-7 interrupts.
• If CSR[MAP] = 1, all caching of memory and the SRAM module are disabled. All
• If CSR[MAP] = 1, all caching of memory and the SRAM module are disabled. All
memory accesses are forced into a specially mapped address space signaled by
TT = 0x2, TM = 0x5 or 0x6. This includes stack frame writes and the vector fetch
for the exception that forced entry into this mode.
TT = 0x2, TM = 0x5 or 0x6. This includes stack frame writes and the vector fetch
for the exception that forced entry into this mode.
The RTE instruction exits emulation mode. The processor status output port provides a
unique encoding for emulator mode entry (0xD) and exit (0x7).
unique encoding for emulator mode entry (0xD) and exit (0x7).
29.6.2 Concurrent BDM and Processor Operation
The debug module supports concurrent operation of both the processor and most BDM
commands. BDM commands may be executed while the processor is running, except those
following operations that access processor/memory registers:
commands. BDM commands may be executed while the processor is running, except those
following operations that access processor/memory registers:
• Read/write address and data registers
• Read/write control registers
• Read/write control registers
For BDM commands that access memory, the debug module requests the processor’s local
bus. The processor responds by stalling the instruction fetch pipeline and waiting for
current bus activity to complete before freeing the local bus for the debug module to
perform its access. After the debug module bus cycle, the processor reclaims the bus.
bus. The processor responds by stalling the instruction fetch pipeline and waiting for
current bus activity to complete before freeing the local bus for the debug module to
perform its access. After the debug module bus cycle, the processor reclaims the bus.
Breakpoint registers must be carefully configured in a development system if the processor
is executing. The debug module contains no hardware interlocks, so TDR should be
disabled while breakpoint registers are loaded, after which TDR can be written to define
the exact trigger. This prevents spurious breakpoint triggers.
is executing. The debug module contains no hardware interlocks, so TDR should be
disabled while breakpoint registers are loaded, after which TDR can be written to define
the exact trigger. This prevents spurious breakpoint triggers.
Because there are no hardware interlocks in the debug unit, no BDM operations are allowed
while the CPU is writing the debug’s registers (DSCLK must be inactive).
Note that the debug module requires the use of the internal bus to perform BDM
commands. In Revision A, if the processor is executing a tight loop that is contained within
a single aligned longword, the processor may never grant the internal bus to the debug
module, for example:
while the CPU is writing the debug’s registers (DSCLK must be inactive).
Note that the debug module requires the use of the internal bus to perform BDM
commands. In Revision A, if the processor is executing a tight loop that is contained within
a single aligned longword, the processor may never grant the internal bus to the debug
module, for example:
align4
label1: nop
bra.b label1
or
align4
label2: bra.w label2
The processor grants the internal bus if these loops are forced across two longwords.