Motorola MCF5281 사용자 설명서

33-20

MCF5282 User’s Manual

MOTOROLA

Fast Ethernet AC Timing Specifications

Table 33-16 lists specifications for the I

C output timing parameters shown in Figure 33-9.

Figure 33-9 shows timing for the valu es in Table 33-15 and T able 33-16.

Figure 33-9. I

C Input/Output Timings

33.12 Fast Ethernet AC Timing Specifications

MII signals use TTL signal levels compatible with devices operating at either 5.0 V or
3.3 V.

Table 33-16. I

C Output Timing Specifications between SCL and SDA

Num

Characteristic

Min

Max

Units

Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed
with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in
Table 33-16. The I

C interface is designed to scale the actual data transition time to move it to

the middle of the SCL low period. The actual position is affected by the prescale and division
values programmed into the IFDR; however, the numbers given in Table 33-16 are minimum
values.

Start condition hold time

—

Bus clocks

Clock low period

—

Bus clocks

Because SCL and SDA are open-collector-type outputs, which the processor can only actively
drive low, the time SCL or SDA take to reach a high level depends on external signal
capacitance and pull-up resistor values.

SCL/SDA rise time (V

= 0.5 V to V

= 2.4 V)

—

µS

Data hold time

—

Bus clocks

Specified at a nominal 50-pF load.

SCL/SDA fall time (V

= 2.4 V to V

= 0.5 V)

—

Clock high time

—

Bus clocks

Data setup time

—

Bus clocks

Start condition setup time (for repeated start
condition only)

—

Bus clocks

Stop condition setup time

—

Bus clocks

SCL

SDA