Motorola MCF5281 사용자 설명서
MOTOROLA
Chapter 33. Electrical Characteristics
33-21
Fast Ethernet AC Timing Specifications
33.12.1 MII Receive Signal Timing (ERXD[3:0], ERXDV,
ERXER, and ERXCLK)
The receiver functions correctly up to a ERXCLK maximum frequency of 25 MHz +1%.
There is no minimum frequency requirement. In addition, the processor clock frequency
must exceed twice the ERXCLK frequency.
There is no minimum frequency requirement. In addition, the processor clock frequency
must exceed twice the ERXCLK frequency.
Table 33-17 lists MII receive channel timings.
Figure 33-10. MII Receive Signal Timing Diagram
33.12.2 MII Transmit Signal Timing (ETXD[3:0], ETXEN,
ETXER, ETXCLK)
The transmitter functions correctly up to a ETXCLK maximum frequency of 25 MHz +1%.
There is no minimum frequency requirement. In addition, the processor clock frequency
must exceed twice the ETXCLK frequency.
There is no minimum frequency requirement. In addition, the processor clock frequency
must exceed twice the ETXCLK frequency.
The transmit outputs (ETXD[3:0], ETXEN, ETXER) can be programmed to transition
from either the rising or falling edge of ETXCLK, and the timing is the same in either case.
This options allows the use of non-compliant MII PHYs. Refer to the Ethernet chapter for
details of this option and how to enable it.
from either the rising or falling edge of ETXCLK, and the timing is the same in either case.
This options allows the use of non-compliant MII PHYs. Refer to the Ethernet chapter for
details of this option and how to enable it.
Table 33-17. MII Receive Signal Timing
Num
Characteristic
1
1
ERXDV, ERXCLK, and ERXD[0] have same timing in 10 Mbps 7-wire interface mode.
Min
Max
Unit
M1
ERXD[3:0], ERXDV, ERXER to ERXCLK setup
5
—
ns
M2
ERXCLK to ERXD[3:0], ERXDV, ERXER hold
5
—
ns
M3
ERXCLK pulse width high
35%
65%
ERXCLK period
M4
ERXCLK pulse width low
35%
65%
ERXCLK period
M1
M2
ERXCLK (input)
ERXD[3:0] (inputs)
ERXDV
ERXER
ERXER
M3
M4