Motorola MVME2300 Series 사용자 설명서
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5-4
Computer Group Literature Center Web Site
Programming Details
5
Notes
1. Interrupt from the PCI/ISA Bridge.
2. Interrupt from the Falcon chip set for a single and/or double bit
memory error.
3. The mapping of interrupt sources from the VMEbus and Universe
internal interrupt sources is programmable via the Local Interrupt
Map 0 Register and the Local Interrupt Map 1 Register in the
Universe ASIC.
Map 0 Register and the Local Interrupt Map 1 Register in the
Universe ASIC.
4. These interrupts also appear at the PIB for backward compatibility
with older MVME1600 and PM603/4 modules.
8259 Interrupts
There are 15 interrupt requests supported by the PIB. These 15 interrupts
are ISA-type interrupts that are functionally equivalent to two 82C59
interrupt controllers. Except for IRQ0, IRQ1, IRQ2, IRQ8_, and IRQ13,
each of the interrupt lines can be configured for either edge-sensitive mode
or level-sensitive mode by programming the appropriate ELCR registers
in the PIB.
are ISA-type interrupts that are functionally equivalent to two 82C59
interrupt controllers. Except for IRQ0, IRQ1, IRQ2, IRQ8_, and IRQ13,
each of the interrupt lines can be configured for either edge-sensitive mode
or level-sensitive mode by programming the appropriate ELCR registers
in the PIB.
There is also support for four PCI interrupts, PIRQ3_-PIRQ0_. The PIB
has four PIRQ Route Control registers to allow each of the PCI interrupt
lines to be routed to any of eleven ISA interrupt lines (IRQ0, IRQ1, IRQ2,
IRQ8_, and IRQ13 are reserved for ISA system interrupts). Since PCI
interrupts are defined as level-sensitive, software must program the
selected IRQ(s) for level-sensitive mode. Note that more than one PCI
has four PIRQ Route Control registers to allow each of the PCI interrupt
lines to be routed to any of eleven ISA interrupt lines (IRQ0, IRQ1, IRQ2,
IRQ8_, and IRQ13 are reserved for ISA system interrupts). Since PCI
interrupts are defined as level-sensitive, software must program the
selected IRQ(s) for level-sensitive mode. Note that more than one PCI
IRQ14
Level
Low
LM/SIG Interrupt 1
4
IRQ15
N/A
N/A
Not used
Table 5-2. RavenMPIC Interrupt Assignments (Continued)
MPIC
IRQ
Edge/
Level
Polarity
Interrupt Source
Notes