사용자 설명서차례Contents7List of Figures15List of Tables17About This Manual19Summary of Changes20Overview of Contents21Comments and Suggestions21Conventions Used in This Manual22Board Description and Memory Maps25Introduction25Overview25Summary of Features26System Block Diagram27Functional Description30VMEbus Interface30Front Panel30PCI interface31P2 I/O31Programming Model31Processor Memory Maps31Default Processor Memory Map32Processor CHRP Memory Map33Processor PREP Memory Map35PCI Configuration Access36PCI Memory Maps37Default PCI Memory Map37PCI CHRP Memory Map37PCI PREP Memory Map40VMEbus Mapping44VMEbus Master Map44VMEbus Slave Map45Falcon-Controlled System Registers48System Configuration Register (SYSCR)49Memory Configuration Register (MEMCR)51System External Cache Control Register (SXCCR)53Processor 0 External Cache Control Register (P0XCCR)54Processor 1 External Cache Control Register (P1XCCR)54CPU Control Register54ISA Local Resource Bus55W83C553 PIB Registers5516550 UART55General-Purpose Readable Jumpers56NVRAM/RTC and Watchdog Timer Registers56Module Configuration and Status Registers57CPU Configuration Register58Base Module Feature Register59Base Module Status Register (BMSR)60Seven-Segment Display Register61VME Registers61LM/SIG Control Register62LM/SIG Status Register63Location Monitor Upper Base Address Register65Location Monitor Lower Base Address Register65Semaphore Register 166Semaphore Register 266VME Geographical Address Register (VGAR)67Emulated Z8536 CIO Registers and Port Pins67Emulated Z8536 Registers67Z8536 CIO Port Pins68ISA DMA Channels69Raven PCI Bridge ASIC71Introduction71Features71Block Diagram72Functional Description74MPC Bus Interface74MPC Address Mapping74MPC Slave76MPC Write Posting78MPC Master78MPC Arbiter80MPC Bus Timer80PCI Interface80PCI Address Mapping81PCI Slave84PCI Write Posting87PCI Master87Generating PCI Cycles91Endian Conversion95When MPC Devices are Big-Endian95When MPC Devices are Little-Endian97Raven Registers and Endian Mode97Error Handling98Transaction Ordering99Raven Registers100MPC Registers100Vendor ID/Device ID Registers102Revision ID Register103General Control-Status/Feature Registers103MPC Arbiter Control Register106Prescaler Adjust Register106MPC Error Enable Register107MPC Error Status Register109MPC Error Address Register110MPC Error Attribute Register - MERAT111PCI Interrupt Acknowledge Register113MPC Slave Address (0,1 and 2) Registers113MPC Slave Address (3) Register114MPC Slave Offset/Attribute (0,1 and 2) Registers115MPC Slave Offset/Attribute (3) Registers116General-Purpose Registers117PCI Registers117Vendor ID/ Device ID Registers119PCI Command/ Status Registers120Revision ID/ Class Code Registers122I/O Base Register122Memory Base Register123PCI Slave Address (0,1,2 and 3) Registers124PCI Slave Attribute/ Offset (0,1,2 and 3) Registers125CONFIG_ADDRESS Register126CONFIG_DATA Register128Raven Interrupt Controller130Features130Architecture130Readability of CSR131Interrupt Source Priority131Processor’s Current Task Priority131Nesting of Interrupt Events132Spurious Vector Generation132Interprocessor Interrupts (IPI)1328259 Compatibility132Raven-Detected Errors133Timers133Interrupt Delivery Modes134Block Diagram Description135Program-Visible Registers136Interrupt Pending Register (IPR)136Interrupt Selector (IS)136Interrupt Request Register (IRR)137In-Service Register (ISR)137Interrupt Router137MPIC Registers139RavenMPIC Registers139Feature Reporting Register143Global Configuration Register144Vendor Identification Register145Processor Init Register145IPI Vector/Priority Registers146Spurious Vector Register147Timer Frequency Register147Timer Current Count Registers148Timer Base Count Registers148Timer Vector/Priority Registers149Timer Destination Registers150External Source Vector/Priority Registers151External Source Destination Registers152Raven-Detected Errors Vector/Priority Register153Raven-Detected Errors Destination Register154Interprocessor Interrupt Dispatch Registers154Interrupt Task Priority Registers155Interrupt Acknowledge Registers156End-of-Interrupt Registers156Programming Notes157External Interrupt Service157Reset State158Interprocessor Interrupts159Dynamically Changing I/O Interrupt Configuration159EOI Register160Interrupt Acknowledge Register1608259 Mode160Current Task Priority Level160Architectural Notes161Falcon ECC Memory Controller Chip Set163Introduction163Features163Block Diagrams164Functional Description167Bit Ordering Convention167Performance167Four-beat Reads/Writes167Single-beat Reads/Writes168DRAM Speeds168ROM/Flash Speeds172PowerPC 60x Bus Interface173Responding to Address Transfers173Completing Data Transfers173Cache Coherency173Cache Coherency Restrictions174L2 Cache Support174ECC174Cycle Types174Error Reporting175Error Logging176DRAM Tester176ROM/Flash Interface176Refresh/Scrub180Blocks A and/or B Present, Blocks C and D Not Present180Blocks A and/or B Present, Blocks C and/or D Present181DRAM Arbitration182Chip Defaults182External Register Set183CSR Accesses183Programming Model183CSR Architecture183Register Summary189Detailed Register Bit Descriptions189Vendor/Device Register192Revision ID/ General Control Register193DRAM Attributes Register195DRAM Base Register197CLK Frequency Register197ECC Control Register198Error Logger Register201Error Address Register204Scrub/Refresh Register205Refresh/Scrub Address Register206ROM A Base/Size Register207ROM B Base/Size Register210DRAM Tester Control Registers21232-Bit Counter212Test SRAM212Power-Up Reset Status Register 1213Power-Up Reset Status Register 2213External Register Set214Software Considerations215Parity Checking on the PowerPC Bus215Programming ROM/Flash Devices215Writing to the Control Registers215Sizing DRAM216ECC Codes219Data Paths222Universe (VMEbus to PCI) Chip225Introduction225Features225Block Diagram227Functional Description227VMEbus Interface228Universe as VMEbus Slave228Universe as VMEbus Master229PCI Bus Interface229Universe as PCI Slave230Universe as PCI Master230Interrupter230VMEbus Interrupt Handling231DMA Controller231Universe Control and Status Registers (UCSR)232Universe Register Map233Universe Chip Problems after PCI Reset238Description238Workarounds239Examples240Example 1: MVME2600 Series Board Exhibits PCI Reset Problem240Example 2: MVME3600 Series Board Acts Differently241Example 3: Universe Chip is Checked at Tundra243Programming Details245Introduction245PCI Arbitration245Interrupt Handling246RavenMPIC2478259 Interrupts248ISA DMA Channels251Exceptions252Sources of Reset252Soft Reset253Universe Chip Problems after PCI Reset253Error Notification and Handling254Endian Issues255Processor/Memory Domain257Role of the Raven ASIC257PCI Domain257PCI-SCSI257PCI/Ethernet257PCI-Graphics258Role of the Universe ASIC258VMEbus Domain258ROM/Flash Initialization259Related Documentation261Motorola Computer Group Documents261Manufacturers’ Documents262Related Specifications264Glossary267Index275크기: 2.61메가바이트페이지: 282Language: English매뉴얼 열기