Motorola MVME2300 Series 사용자 설명서
1-12
Computer Group Literature Center Web Site
Board Description and Memory Maps
1
4. The first Megabyte of ROM/Flash bank A appears at this range after
a reset if the rom_b_rv control bit is cleared. If the rom_b_rv control
bit is set then this address range maps to ROM/Flash bank B.
bit is set then this address range maps to ROM/Flash bank B.
5. This range can be mapped to the VMEbus by programming the
Universe ASIC accordingly.
6. The only method of generating a PCI Interrupt Acknowledge cycle
(8259 IACK) is to perform a read access to the Raven’s PIACK
register at 0xFEFF0030.
register at 0xFEFF0030.
The following table shows the programmed values for the associated
Raven MPC registers for the processor PREP memory map.
Raven MPC registers for the processor PREP memory map.
PCI Configuration Access
PCI Configuration accesses are accomplished via the CONFIG_ADD and
CONFIG_DAT registers. These two registers are implemented in the
Raven ASIC. In the CHRP memory map example, the CONFIG_ADD and
CONFIG_DAT registers are located at 0xFE000CF8 and 0xFE000CFC,
respectively. With the PREP memory map, the CONFIG_ADD register
and the CONFIG_DAT register are located at 0x80000CF8 and
0x80000CFC, respectively.
CONFIG_DAT registers. These two registers are implemented in the
Raven ASIC. In the CHRP memory map example, the CONFIG_ADD and
CONFIG_DAT registers are located at 0xFE000CF8 and 0xFE000CFC,
respectively. With the PREP memory map, the CONFIG_ADD register
and the CONFIG_DAT register are located at 0x80000CF8 and
0x80000CFC, respectively.
Table 1-6. Raven MPC Register Values for PREP Memory Map
Address
Register Name
Register Value
FEFF 0040
MSADD0
C000 FCFF
FEFF 0044
MSOFF0 & MSATT0
4000 00C2
FEFF 0048
MSADD1
0000 0000
FEFF 004C
MSOFF1 & MSATT1
0000 0002
FEFF 0050
MSADD2
0000 0000
FEFF 0054
MSOFF2 & MSATT2
0000 0002
FEFF 0058
MSADD3
8000 BFFF
FEFF 005C
MSOFF3 & MSATT3
8000 00C0