Motorola MVME2300 Series 사용자 설명서
Functional Description
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The PCI interface may operate at any clock speed up to 33MHz. The
PCLK input must be externally synchronized with the MCLK input, and
the frequency of the PCLK input must be exactly half the frequency of the
MCLK input.
PCLK input must be externally synchronized with the MCLK input, and
the frequency of the PCLK input must be exactly half the frequency of the
MCLK input.
PCI Address Mapping
The Raven ASIC provides three resources to PCI:
❏
Configuration registers mapped into PCI Configuration space
❏
MPC bus address space mapped into PCI Memory space
❏
RavenMPIC control registers mapped into either PCI I/O space or
PCI Memory space
PCI Memory space
Configuration Registers
The Raven has no IDSEL pin. Instead, an internal connection made within
the Raven logically associates the assertion of IDSEL with the assertion of
AD31.
the Raven logically associates the assertion of IDSEL with the assertion of
AD31.
Raven provides a configuration space that is fully compliant with the PCI
Local Bus Specification 2.0 definition for configuration space. Two base
registers within the standard 64-byte header are used to control the
mapping of RavenMPIC. One register is dedicated to mapping
RavenMPIC into PCI I/O space; the other register is dedicated to mapping
RavenMPIC into PCI Memory space. The mapping of MPC address space
is handled by device-specific registers located above the 64-byte header.
These control registers support a mapping scheme that is functionally
similar to the PCI-to-MPC mapping scheme described in the section on
Local Bus Specification 2.0 definition for configuration space. Two base
registers within the standard 64-byte header are used to control the
mapping of RavenMPIC. One register is dedicated to mapping
RavenMPIC into PCI I/O space; the other register is dedicated to mapping
RavenMPIC into PCI Memory space. The mapping of MPC address space
is handled by device-specific registers located above the 64-byte header.
These control registers support a mapping scheme that is functionally
similar to the PCI-to-MPC mapping scheme described in the section on
earlier in this chapter.