Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 데이터 시트

Datasheet

101

B/D/F/Type:

0/0/0/MCHBAR

Address Offset: 200–201h

Default Value:

0000h

Access:

RO, RW/L 

Size:

16 bits

The DRAM Rank Boundary Registers define the upper boundary address of each DRAM 

rank with a granularity of 64MB. Each rank has its own single-word DRB register. These 

registers are used to determine which chip select will be active for a given address. 

Channel and rank map:

ch0 rank0:

200h

ch0 rank1:

202h

ch0 rank2:

204h

ch0 rank3:

206h

ch1 rank0:

600h

ch1 rank1:

602h

ch1 rank2:

604h

ch1 rank3:

606h

If Channel 0 is empty, all of the C0DRBs are programmed with 00h.

C0DRB0 = Total memory in ch0 rank0 (in 64MB increments)

C0DRB1 = Total memory in ch0 rank0 + ch0 rank1 (in 64MB increments)

and so on.

If Channel 1 is empty, all of the C1DRBs are programmed with 00h.

C1DRB0 = Total memory in ch1 rank0 (in 64MB increments)

C1DRB1 = Total memory in ch1 rank0 + ch1 rank1 (in 64MB increments)

and so on.

CODRBs: 

Similar to Non-stacked mode.

C1DRB0, C1DRB1 and C1DRB2:

They are also programmed similar to non-stacked mode. Only exception is, the DRBs 

corresponding to the topmost populated rank and the (unpopulated) higher ranks in 

Channel 1 must be programmed with the value of the total Channel 1 population plus 

the value of total Channel 0 population (C0DRB3).

Example: If only ranks 0 and 1 are populated in Ch1 in stacked mode, then 

C1DRB0 = Total memory in ch1 rank0 (in 64MB increments)