Intel Xeon Wolfdale E3210 사용자 매뉴얼

차례

• Intel® 3200 and 3210 Chipset

  1
  • Contents

    3
    • Figures

      11
    • Tables

      11
  • Revision History

    13
• 1 Introduction

  15
  • 1.1 Terminology

    17
  • 1.2 MCH Overview

    20
    • 1.2.1 Host Interface

      20
    • 1.2.2 System Memory Interface

      20
    • 1.2.3 Direct Media Interface (DMI)

      21
    • 1.2.4 PCI Express* Interface

      22
    • 1.2.5 MCH Clocking

      23
    • 1.2.6 Power Management

      23
    • 1.2.7 Thermal Sensor

      23
• 2 Signal Description

  25
  • 2.1 Host Interface Signals

    26
  • 2.2 System Memory (DDR2) Interface Signals

    29
    • 2.2.1 System Memory Channel A Interface Signals

      29
    • 2.2.2 System Memory Channel B Interface Signals

      30
    • 2.2.3 System Memory Miscellaneous Signals

      31
  • 2.3 PCI Express* Interface Signals

    31
  • 2.4 Controller Link Interface Signals

    32
  • 2.5 Clocks, Reset, and Miscellaneous

    32
  • 2.6 Direct Media Interface

    33
  • 2.7 Power and Grounds

    34
• 3 System Address Map

  35
  • 3.1 Legacy Address Range

    38
    • 3.1.1 DOS Range (0h - 9_FFFFh)

      38
    • 3.1.2 Expansion Area (C_0000h-D_FFFFh)

      39
    • 3.1.3 Extended System BIOS Area (E_0000h-E_FFFFh)

      39
    • 3.1.4 System BIOS Area (F_0000h-F_FFFFh)

      40
    • 3.1.5 PAM Memory Area Details

      40
  • 3.2 Main Memory Address Range (1MB - TOLUD)

    40
    • 3.2.1 ISA Hole (15 MB -16 MB)

      41
    • 3.2.2 TSEG

      42
    • 3.2.3 Pre-allocated Memory

      42
  • 3.3 PCI Memory Address Range (TOLUD - 4 GB)

    43
    • 3.3.1 APIC Configuration Space (FEC0_0000h-FECF_FFFFh)

      45
    • 3.3.2 HSEG (FEDA_0000h-FEDB_FFFFh)

      45
    • 3.3.3 FSB Interrupt Memory Space (FEE0_0000-FEEF_FFFF)

      45
    • 3.3.4 High BIOS Area

      45
  • 3.4 Main Memory Address Space (4 GB to TOUUD)

    46
    • 3.4.1 Memory Re-claim Background

      47
    • 3.4.2 Memory Reclaiming

      47
  • 3.5 PCI Express* Configuration Address Space

    47
  • 3.6 PCI Express* Address Space

    48
  • 3.7 System Management Mode (SMM)

    49
    • 3.7.1 SMM Space Definition

      49
    • 3.7.2 SMM Space Restrictions

      50
    • 3.7.3 SMM Space Combinations

      50
    • 3.7.4 SMM Control Combinations

      51
    • 3.7.5 SMM Space Decode and Transaction Handling

      51
    • 3.7.6 Processor WB Transaction to an Enabled SMM Address Space

      51
    • 3.7.7 SMM Access Through TLB

      51
  • 3.8 Memory Shadowing

    52
  • 3.9 I/O Address Space

    52
    • 3.9.1 PCI Express* I/O Address Mapping

      53
• 4 MCH Register Description

  55
  • 4.1 Register Terminology

    56
  • 4.2 Configuration Process and Registers

    57
    • 4.2.1 Platform Configuration Structure

      57
  • 4.3 Configuration Mechanisms

    58
    • 4.3.1 Standard PCI Configuration Mechanism

      58
    • 4.3.2 PCI Express Enhanced Configuration Mechanism

      59
  • 4.4 Routing Configuration Accesses

    60
    • 4.4.1 Internal Device Configuration Accesses

      61
    • 4.4.2 Bridge Related Configuration Accesses

      62
  • 4.5 I/O Mapped Registers

    63
    • 4.5.1 CONFIG_ADDRESS-Configuration Address Register

      63
    • 4.5.2 CONFIG_DATA-Configuration Data Register

      64
• 5 DRAM Controller Registers (D0:F0)

  65
  • 5.1 Configuration Register Details

    67
    • 5.1.1 VID-Vendor Identification

      67
    • 5.1.2 DID-Device Identification

      67
    • 5.1.3 PCICMD-PCI Command

      68
    • 5.1.4 PCISTS-PCI Status

      69
    • 5.1.5 RID-Revision Identification

      70
    • 5.1.6 CC-Class Code

      70
    • 5.1.7 MLT-Master Latency Timer

      70
    • 5.1.8 HDR-Header Type

      71
    • 5.1.9 SVID-Subsystem Vendor Identification

      71
    • 5.1.10 SID-Subsystem Identification

      71
    • 5.1.11 CAPPTR-Capabilities Pointer

      72
    • 5.1.12 PXPEPBAR-PCI Express* Egress Port Base Address

      72
    • 5.1.13 MCHBAR-MCH Memory Mapped Register Range Base

      73
    • 5.1.14 DEVEN-Device Enable

      74
    • 5.1.15 PCIEXBAR-PCI Express* Register Range Base Address

      75
    • 5.1.16 DMIBAR-Root Complex Register Range Base Address

      77
    • 5.1.17 PAM0-Programmable Attribute Map 0

      78
    • 5.1.18 PAM1-Programmable Attribute Map 1

      79
    • 5.1.19 PAM2-Programmable Attribute Map 2

      80
    • 5.1.20 PAM3-Programmable Attribute Map 3

      81
    • 5.1.21 PAM4-Programmable Attribute Map 4

      82
    • 5.1.22 PAM5-Programmable Attribute Map 5

      83
    • 5.1.23 PAM6-Programmable Attribute Map 6

      84
    • 5.1.24 LAC-Legacy Access Control

      84
    • 5.1.25 REMAPBASE-Remap Base Address Register

      85
    • 5.1.26 REMAPLIMIT-Remap Limit Address Register

      85
    • 5.1.27 SMRAM-System Management RAM Control

      86
    • 5.1.28 ESMRAMC-Extended System Management RAM Control

      87
    • 5.1.29 TOM-Top of Memory

      88
    • 5.1.30 TOUUD-Top of Upper Usable Dram

      88
    • 5.1.31 BSM-Base of Stolen Memory

      89
    • 5.1.32 TSEGMB-TSEG Memory Base

      89
    • 5.1.33 TOLUD-Top of Low Usable DRAM

      90
    • 5.1.34 ERRSTS-Error Status

      91
    • 5.1.35 ERRCMD-Error Command

      93
    • 5.1.36 SMICMD-SMI Command

      94
    • 5.1.37 SKPD-Scratchpad Data

      94
    • 5.1.38 CAPID0-Capability Identifier

      95
  • 5.2 MCHBAR

    98
    • 5.2.1 CHDECMISC-Channel Decode Misc

      100
    • 5.2.2 C0DRB0-Channel 0 DRAM Rank Boundary Address 0

      101
    • 5.2.3 C0DRB1-Channel 0 DRAM Rank Boundary Address 1

      102
    • 5.2.4 C0DRB2-Channel 0 DRAM Rank Boundary Address 2

      103
    • 5.2.5 C0DRB3-Channel 0 DRAM Rank Boundary Address 3

      103
    • 5.2.6 C0DRA01-Channel 0 DRAM Rank 0,1 Attribute

      104
    • 5.2.7 C0DRA23-Channel 0 DRAM Rank 2,3 Attribute

      105
    • 5.2.8 C0CYCTRKPCHG-Channel 0 CYCTRK PCHG

      105
    • 5.2.9 C0CYCTRKACT-Channel 0 CYCTRK ACT

      106
    • 5.2.10 C0CYCTRKWR-Channel 0 CYCTRK WR

      107
    • 5.2.11 C0CYCTRKRD-Channel 0 CYCTRK READ

      108
    • 5.2.12 C0CYCTRKREFR-Channel 0 CYCTRK REFR

      108
    • 5.2.13 C0CKECTRL-Channel 0 CKE Control

      109
    • 5.2.14 C0REFRCTRL-Channel 0 DRAM Refresh Control

      110
    • 5.2.15 C0ECCERRLOG-Channel 0 ECC Error Log

      112
    • 5.2.16 C0ODTCTRL-Channel 0 ODT Control

      113
    • 5.2.17 C1DRB0-Channel 1 DRAM Rank Boundary Address 0

      113
    • 5.2.18 C1DRB1-Channel 1 DRAM Rank Boundary Address 1

      114
    • 5.2.19 C1DRB2-Channel 1 DRAM Rank Boundary Address 2

      114
    • 5.2.20 C1DRB3-Channel 1 DRAM Rank Boundary Address 3

      115
    • 5.2.21 C1DRA01-Channel 1 DRAM Rank 0,1 Attributes

      115
    • 5.2.22 C1DRA23-Channel 1 DRAM Rank 2,3 Attributes

      115
    • 5.2.23 C1CYCTRKPCHG-Channel 1 CYCTRK PCHG

      116
    • 5.2.24 C1CYCTRKACT-Channel 1 CYCTRK ACT

      117
    • 5.2.25 C1CYCTRKWR-Channel 1 CYCTRK WR

      118
    • 5.2.26 C1CYCTRKRD-Channel 1 CYCTRK READ

      118
    • 5.2.27 C1CKECTRL-Channel 1 CKE Control

      119
    • 5.2.28 C1REFRCTRL-Channel 1 DRAM Refresh Control

      120
    • 5.2.29 C1ECCERRLOG-Channel 1 ECC Error Log

      121
    • 5.2.30 C1ODTCTRL-Channel 1 ODT Control

      122
    • 5.2.31 EPC0DRB0-EP Channel 0 DRAM Rank Boundary Address 0

      123
    • 5.2.32 EPC0DRB1-EP Channel 0 DRAM Rank Boundary Address 1

      123
    • 5.2.33 EPC0DRB2-EP Channel 0 DRAM Rank Boundary Address 2

      123
    • 5.2.34 EPC0DRB3-EP Channel 0 DRAM Rank Boundary Address 3

      124
    • 5.2.35 EPC0DRA01-EP Channel 0 DRAM Rank 0,1 Attribute

      124
    • 5.2.36 EPC0DRA23-EP Channel 0 DRAM Rank 2,3 Attribute

      125
    • 5.2.37 EPDCYCTRKWRTPRE-EPD CYCTRK WRT PRE

      125
    • 5.2.38 EPDCYCTRKWRTACT-EPD CYCTRK WRT ACT

      126
    • 5.2.39 EPDCYCTRKWRTWR-EPD CYCTRK WRT WR

      126
    • 5.2.40 EPDCYCTRKWRTREF-EPD CYCTRK WRT REF

      127
    • 5.2.41 EPDCYCTRKWRTRD-EPD CYCTRK WRT READ

      127
    • 5.2.42 EPDCKECONFIGREG-EPD CKE Related Configuration

      128
    • 5.2.43 EPDREFCONFIG-EP DRAM Refresh Configuration

      129
    • 5.2.44 TSC1-Thermal Sensor Control 1

      131
    • 5.2.45 TSC2-Thermal Sensor Control 2

      132
    • 5.2.46 TSS-Thermal Sensor Status

      134
    • 5.2.47 TSTTP-Thermal Sensor Temperature Trip Point

      135
    • 5.2.48 TCO-Thermal Calibration Offset

      136
    • 5.2.49 THERM1-Thermal Hardware Protection

      137
    • 5.2.50 TIS-Thermal Interrupt Status

      137
    • 5.2.51 TSMICMD-Thermal SMI Command

      139
    • 5.2.52 PMSTS-Power Management Status

      140
  • 5.3 EPBAR

    141
    • 5.3.1 EPESD-EP Element Self Description

      141
    • 5.3.2 EPLE1D-EP Link Entry 1 Description

      142
    • 5.3.3 EPLE1A-EP Link Entry 1 Address

      142
    • 5.3.4 EPLE2D-EP Link Entry 2 Description

      143
    • 5.3.5 EPLE2A-EP Link Entry 2 Address

      143
    • 5.3.6 EPLE3D-EP Link Entry 3 Description

      144
    • 5.3.7 EPLE3A-EP Link Entry 3 Address

      145
• 6 Host-Primary PCI Express* Bridge Registers (D1:F0)

  147
  • 6.1 VID1-Vendor Identification

    149
  • 6.2 DID1-Device Identification

    150
  • 6.3 PCICMD1-PCI Command

    150
  • 6.4 PCISTS1-PCI Status

    152
  • 6.5 RID1-Revision Identification

    153
  • 6.6 CC1-Class Code

    153
  • 6.7 CL1-Cache Line Size

    154
  • 6.8 HDR1-Header Type

    154
  • 6.9 PBUSN1-Primary Bus Number

    154
  • 6.10 SBUSN1-Secondary Bus Number

    155
  • 6.11 SUBUSN1-Subordinate Bus Number

    155
  • 6.12 IOBASE1-I/O Base Address

    156
  • 6.13 IOLIMIT1-I/O Limit Address

    156
  • 6.14 SSTS1-Secondary Status

    157
  • 6.15 MBASE1-Memory Base Address

    158
  • 6.16 MLIMIT1-Memory Limit Address

    159
  • 6.17 PMBASE1-Prefetchable Memory Base Address

    160
  • 6.18 PMLIMIT1-Prefetchable Memory Limit Address

    161
  • 6.19 PMBASEU1-Prefetchable Memory Base Address Upper

    162
  • 6.20 PMLIMITU1-Prefetchable Memory Limit Address Upper

    163
  • 6.21 CAPPTR1-Capabilities Pointer

    163
  • 6.22 INTRLINE1-Interrupt Line

    164
  • 6.23 INTRPIN1-Interrupt Pin

    164
  • 6.24 BCTRL1-Bridge Control

    164
  • 6.25 PM_CAPID1-Power Management Capabilities

    166
  • 6.26 PM_CS1-Power Management Control/Status

    167
  • 6.27 SS_CAPID-Subsystem ID and Vendor ID Capabilities

    168
  • 6.28 SS-Subsystem ID and Subsystem Vendor ID

    168
  • 6.29 MSI_CAPID-Message Signaled Interrupts Capability ID

    169
  • 6.30 MC-Message Control

    169
  • 6.31 MA-Message Address

    170
  • 6.32 MD-Message Data

    170
  • 6.33 PE_CAPL-PCI Express* Capability List

    170
  • 6.34 PE_CAP-PCI Express* Capabilities

    171
  • 6.35 DCAP-Device Capabilities

    171
  • 6.36 DCTL-Device Control

    172
  • 6.37 DSTS-Device Status

    173
  • 6.38 LCAP-Link Capabilities

    174
  • 6.39 LCTL-Link Control

    176
  • 6.40 LSTS-Link Status

    178
  • 6.41 SLOTCAP-Slot Capabilities

    179
  • 6.42 SLOTCTL-Slot Control

    180
  • 6.43 SLOTSTS-Slot Status

    182
  • 6.44 RCTL-Root Control

    183
  • 6.45 RSTS-Root Status

    184
  • 6.46 PELC-PCI Express Legacy Control

    184
  • 6.47 VCECH-Virtual Channel Enhanced Capability Header

    185
  • 6.48 PVCCAP1-Port VC Capability Register 1

    185
  • 6.49 PVCCAP2-Port VC Capability Register 2

    186
  • 6.50 PVCCTL-Port VC Control

    186
  • 6.51 VC0RCAP-VC0 Resource Capability

    187
  • 6.52 VC0RCTL-VC0 Resource Control

    188
  • 6.53 VC0RSTS-VC0 Resource Status

    189
  • 6.54 RCLDECH-Root Complex Link Declaration Enhanced

    189
  • 6.55 ESD-Element Self Description

    190
  • 6.56 LE1D-Link Entry 1 Description

    190
  • 6.57 LE1A-Link Entry 1 Address

    191
  • 6.58 PESSTS-PCI Express* Sequence Status

    191
• 7 Intel Manageability Engine Subsystem PCI (D3:F0,F3)

  193
  • 7.1 HECI Function in ME Subsystem (D3:F0)

    193
    • 7.1.1 ID-Identifiers

      194
    • 7.1.2 CMD-Command

      194
    • 7.1.3 STS-Device Status

      195
    • 7.1.4 RID-Revision ID

      195
    • 7.1.5 CC-Class Code

      195
    • 7.1.6 CLS-Cache Line Size

      196
    • 7.1.7 MLT-Master Latency Timer

      196
    • 7.1.8 HTYPE-Header Type

      196
    • 7.1.9 HECI_MBAR-HECI MMIO Base Address

      197
    • 7.1.10 SS-Sub System Identifiers

      197
    • 7.1.11 CAP-Capabilities Pointer

      198
    • 7.1.12 INTR-Interrupt Information

      198
    • 7.1.13 MGNT-Minimum Grant

      198
    • 7.1.14 MLAT-Maximum Latency

      199
    • 7.1.15 HFS-Host Firmware Status

      199
    • 7.1.16 PID-PCI Power Management Capability ID

      199
    • 7.1.17 PC-PCI Power Management Capabilities

      200
    • 7.1.18 PMCS-PCI Power Management Control And Status

      200
    • 7.1.19 MID-Message Signaled Interrupt Identifiers

      201
    • 7.1.20 MC-Message Signaled Interrupt Message Control

      201
    • 7.1.21 MA-Message Signaled Interrupt Message Address

      202
    • 7.1.22 MUA-Message Signaled Interrupt Upper Address (Optional)

      202
    • 7.1.23 MD-Message Signaled Interrupt Message Data

      202
    • 7.1.24 HIDM-HECI Interrupt Delivery Mode

      203
  • 7.2 KT IO/ Memory Mapped Device Specific Registers [D3:F3]

    204
    • 7.2.1 KTRxBR-KT Receive Buffer

      204
    • 7.2.2 KTTHR-KT Transmit Holding

      205
    • 7.2.3 KTDLLR-KT Divisor Latch LSB

      205
    • 7.2.4 KTIER-KT Interrupt Enable

      206
    • 7.2.5 KTDLMR-KT Divisor Latch MSB

      206
    • 7.2.6 KTIIR-KT Interrupt Identification

      207
    • 7.2.7 KTFCR-KT FIFO Control

      208
    • 7.2.8 KTLCR-KT Line Control

      209
    • 7.2.9 KTMCR-KT Modem Control

      210
    • 7.2.10 KTLSR-KT Line Status

      211
    • 7.2.11 KTMSR-KT Modem Status

      212
    • 7.2.12 KTSCR-KT Scratch

      212
• 8 Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only)

  213
  • 8.1 VID1-Vendor Identification

    215
  • 8.2 DID1-Device Identification

    216
  • 8.3 PCICMD1-PCI Command

    216
  • 8.4 PCISTS1-PCI Status

    218
  • 8.5 RID1-Revision Identification

    219
  • 8.6 CC1-Class Code

    219
  • 8.7 CL1-Cache Line Size

    220
  • 8.8 HDR1-Header Type

    220
  • 8.9 PBUSN1-Primary Bus Number

    220
  • 8.10 SBUSN1-Secondary Bus Number

    221
  • 8.11 SUBUSN1-Subordinate Bus Number

    221
  • 8.12 IOBASE1-I/O Base Address

    222
  • 8.13 IOLIMIT1-I/O Limit Address

    222
  • 8.14 SSTS1-Secondary Status

    223
  • 8.15 MBASE1-Memory Base Address

    224
  • 8.16 MLIMIT1-Memory Limit Address

    225
  • 8.17 PMBASE1-Prefetchable Memory Base Address Upper

    226
  • 8.18 PMLIMIT1-Prefetchable Memory Limit Address

    227
  • 8.19 PMBASEU1-Prefetchable Memory Base Address Upper

    228
  • 8.20 PMLIMITU1-Prefetchable Memory Limit Address Upper

    229
  • 8.21 CAPPTR1-Capabilities Pointer

    230
  • 8.22 INTRLINE1-Interrupt Line

    230
  • 8.23 INTRPIN1-Interrupt Pin

    230
  • 8.24 BCTRL1-Bridge Control

    231
  • 8.25 PM_CAPID1-Power Management Capabilities

    232
  • 8.26 PM_CS1-Power Management Control/Status

    233
  • 8.27 SS_CAPID-Subsystem ID and Vendor ID Capabilities

    234
  • 8.28 SS-Subsystem ID and Subsystem Vendor ID

    234
  • 8.29 MSI_CAPID-Message Signaled Interrupts Capability ID

    235
  • 8.30 MC-Message Control

    235
  • 8.31 MA-Message Address

    236
  • 8.32 MD-Message Data

    236
  • 8.33 PE_CAPL-PCI Express* Capability List

    236
  • 8.34 PE_CAP-PCI Express* Capabilities

    237
  • 8.35 DCAP-Device Capabilities

    237
  • 8.36 DCTL-Device Control

    238
  • 8.37 DSTS-Device Status

    239
  • 8.38 LCAP-Link Capabilities

    240
  • 8.39 LCTL-Link Control

    242
  • 8.40 LSTS-Link Status

    244
  • 8.41 SLOTCAP-Slot Capabilities

    245
  • 8.42 SLOTCTL-Slot Control

    246
  • 8.43 SLOTSTS-Slot Status

    248
  • 8.44 RCTL-Root Control

    249
  • 8.45 RSTS-Root Status

    250
  • 8.46 PELC-PCI Express Legacy Control

    250
  • 8.47 VCECH-Virtual Channel Enhanced Capability Header

    251
  • 8.48 PVCCAP1-Port VC Capability Register 1

    251
  • 8.49 PVCCAP2-Port VC Capability Register 2

    252
  • 8.50 PVCCTL-Port VC Control

    252
  • 8.51 VC0RCAP-VC0 Resource Capability

    253
  • 8.52 VC0RCTL-VC0 Resource Control

    254
  • 8.53 VC0RSTS-VC0 Resource Status

    255
  • 8.54 RCLDECH-Root Complex Link Declaration Enhanced

    255
  • 8.55 ESD-Element Self Description

    256
  • 8.56 LE1D-Link Entry 1 Description

    257
  • 8.57 LE1A-Link Entry 1 Address

    257
• 9 Direct Media Interface (DMI) RCRB

  259
  • 9.1 DMIVCECH-DMI Virtual Channel Enhanced Capability

    260
  • 9.2 DMIPVCCAP1-DMI Port VC Capability Register 1

    260
  • 9.3 DMIPVCCTL-DMI Port VC Control

    261
  • 9.4 DMIVC0RCAP-DMI VC0 Resource Capability

    261
  • 9.5 DMIVC0RCTL0-DMI VC0 Resource Control

    262
  • 9.6 DMIVC0RSTS-DMI VC0 Resource Status

    263
  • 9.7 DMIVC1RCAP-DMI VC1 Resource Capability

    263
  • 9.8 DMIVC1RCTL1-DMI VC1 Resource Control

    264
  • 9.9 DMIVC1RSTS-DMI VC1 Resource Status

    265
  • 9.10 DMILCAP-DMI Link Capabilities

    265
  • 9.11 DMILCTL-DMI Link Control

    266
  • 9.12 DMILSTS-DMI Link Status

    266
• 10 Functional Description

  267
  • 10.1 Host Interface

    267
    • 10.1.1 FSB IOQ Depth

      267
    • 10.1.2 FSB OOQ Depth

      267
    • 10.1.3 FSB GTL+ Termination

      267
    • 10.1.4 FSB Dynamic Bus Inversion

      267
    • 10.1.5 APIC Cluster Mode Support

      268
  • 10.2 System Memory Controller

    269
    • 10.2.1 System Memory Organization Modes

      269
    • 10.2.2 System Memory Technology Supported

      270
    • 10.2.3 Error Checking and Correction

      271
  • 10.3 PCI Express*

    274
    • 10.3.1 PCI Express* Architecture

      274
  • 10.4 Thermal Sensor

    275
    • 10.4.1 PCI Device 0, Function 0

      275
    • 10.4.2 MCHBAR Thermal Sensor Registers

      275
  • 10.5 Power Management

    276
  • 10.6 Clocking

    276
• 11 Electrical Characteristics

  279
  • 11.1 Absolute Minimum and Maximum Ratings

    279
  • 11.2 Current Consumption

    281
  • 11.3 Signal Groups

    282
  • 11.4 Buffer Supply and DC Characteristics

    285
    • 11.4.1 I/O Buffer Supply Voltages

      285
    • 11.4.2 General DC Characteristics

      286
• 12 Ballout and Package Information

  289
  • 12.1 Ballout Information

    289
  • 12.2 Package Information

    313
• 13 Testability

  315
  • 13.1 XOR Test Mode Initialization

    315
  • 13.2 XOR Chain Definition

    316
  • 13.3 XOR Chains

    317
  • 13.4 XOR Chains

    318