Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 데이터 시트

316

Datasheet

The above figure shows the wave forms to be able to boot the part into XOR mode. The 

straps that need to be controlled during this boot process are BSEL[2:0], RSVD (Ball 

L18), EXP_SLR, and XORTEST.

On the 3200 and 3210 Chipset platforms, all strap values must be driven before 

PWROK asserts. BSEL0 must be a 1. BSEL[2:1] need to be defined values, but logic 

value in any order will do. XORTEST must be driven to 0. 

Not all of the pins will be used in all implementations. Due to the need to minimize test 

points and unnecessary routing, the XOR Chain 14 is dynamic depending on the values 

of EXP_SLR, and RSVD (Ball L18). See 

 for what parts of XOR Chain 14 

become valid XOR inputs depending on the use of EXP_SLR and RSVD (Ball L18).

The MCH has 15 XOR chains. The XOR chain outputs are driven out on the following 

output pins. During fullwidth testing, XOR chain outputs will be visible on both pins. 

1

0

EXP_RXP[15:0]

EXP_RXN[15:0]

EXP_TXP[15:0]

EXP_TXN[15:0]

1

1

EXP_RXP[15:0]

EXP_RXN[15:0]

EXP_TXP[15:0]

EXP_TXN[15:0]

0

0

EXP_RXP[15:8]

EXP_RXN[15:8]

EXP_TXP[15:8]

EXP_TXN[15:8]

0

1

EXP_RXP[7:0]

EXP_RXN[7:0]

EXP_TXP[7:0]

EXP_TXN[7:0]

1

0

EXP_RXP[15:0]

EXP_RXN[15:0]

EXP_TXP[15:0]

EXP_TXN[15:0]

1

1

EXP_RXP[15:0]

EXP_RXN[15:0]

EXP_TXP[15:0]

EXP_TXN[15:0]