HP Intel Xeon W3550 VF152AV 사용자 설명서
제품 코드
VF152AV
Intel® Xeon® Processor 3500 Series Datasheet, Volume 2
49
Register Description
2.8.2
MC_STATUS
This register is the MC primary status register.
Device:
3
Function: 0
Offset:
4Ch
Access as a Dword
Bit
Type
Reset
Value
Description
4
RO
1
ECC_ENABLED. ECC is enabled.
2
RO
0
CHANNEL2_DISABLED
Channel 2 is disabled. This can be factory configured or if Init done is written
Channel 2 is disabled. This can be factory configured or if Init done is written
without the channel_active being set. Clocks in the channel will be disabled
when this bit is set.
1
RO
0
CHANNEL1_DISABLED
Channel 1 is disabled. This can be factory configured or if Init done is written
Channel 1 is disabled. This can be factory configured or if Init done is written
without the channel_active being set. Clocks in the channel will be disabled
when this bit is set.
0
RO
0
CHANNEL0_DISABLED
Channel 0 is disabled. This can be factory configured or if Init done is written
Channel 0 is disabled. This can be factory configured or if Init done is written
without the channel_active being set. Clocks in the channel will be disabled
when this bit is set.