Samsung 1GB 400MHz DDR M368L2923DUN-CCC 전단

제품 코드
M368L2923DUN-CCC
다운로드
페이지 25
DDR SDRAM
256MB, 512MB, 1GB Unbuffered DIMM
Rev. 0.1 June 2005
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Speed @CL2
-
133MHz
Speed @CL2.5
166MHz
166MHz
Speed @CL3
200MHz
-
CL-tRCD-tRP
3-3-3
2.5-3-3
184Pin Unbuffered DIMM based on 512Mb C-die (x8, x16)
• VDD : 2.5V ± 0.2V, VDDQ :  2.5V ± 0.2V for DDR333 
• VDD : 2.6V ± 0.1V, VDDQ :  2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe  [DQ] (x4,x8)  &  [L(U)DQS] (x16) 
• Differential clock inputs(CK and CK)
• DLL aligns  DQ and DQS transition with CK transition
• Programmable Read latency : DDR333(2.5 Clock), DDR400(3 Clock)
• Programmable  Burst length (2, 4, 8)
• Programmable  Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) 
• Serial presence detect with EEPROM
• PCB : Height 1,250 (mil) & single (256, 512MB), double (1GB) sided  
• SSTL_2 Interface
• 66pin TSOP II 
Pb-Free 
package
 RoHS compliant
1.0 Ordering Information
2.0 Operating Frequencies
Part Number
Density
Organization
Component Composition
Height
M368L3324DUS-C(L)CC/B3
256MB
32M x 64
      32Mx16 (K4H511638D) * 4EA
1,250mil
M368L6523DUS-C(L)CC/B3
512MB
64M x 64
      64Mx8 (K4H510838D) * 8EA
1,250mil
M381L6523DUM-C(L)CC/B3
512MB
64M x 72
      64Mx8 (K4H510838D) * 9EA
1,250mil
M368L2923DUN-C(L)CC/B3
1GB
128M x 64
      64Mx8 (K4H510838D) * 16EA
1,250mil
M381L2923DUM-C(L)CC/B3
1GB
128M x 72
      64Mx8 (K4H510838D) * 18EA
1,250mil
3.0 Feature