Intel Xeon L3406 CM80616005010AA 사용자 설명서
제품 코드
CM80616005010AA
System Address Map
284
Datasheet, Volume 2
5.2.5.2
MMIOL
This region is used for PCIe device memory addressing below 4 GB. Each IIO in the
system is allocated a portion of this address range and individual PCIe ports and other
integrated devices within an IIO (for example, VTBAR) use sub-portions within that
range. There are IIO-specific requirements on how software allocates this system
region amongst IIOs to support of peer-to-peer between IIOs. Refer to
system is allocated a portion of this address range and individual PCIe ports and other
integrated devices within an IIO (for example, VTBAR) use sub-portions within that
range. There are IIO-specific requirements on how software allocates this system
region amongst IIOs to support of peer-to-peer between IIOs. Refer to
for details of these restrictions. Each IIO has a couple of MMIOL address range registers
(LMMIOL and GMMIOL) to support local peer-to-peer in the MMIOL address range.
Refer to
(LMMIOL and GMMIOL) to support local peer-to-peer in the MMIOL address range.
Refer to
outbound MMIOL range decoding.
5.2.5.3
Miscellaneous
This region is used by the processor for miscellaneous functionality including an
address range that software can write to generate CPEI message on Intel QuickPath
Interconnect, and so forth. IIO aborts all inbound accesses to this region. Outbound
accesses to this region is not explicitly decoded by IIO and are forwarded to
downstream subtractive decode port, if one exists, by virtue of subtractive decoding
else it is master aborted.
address range that software can write to generate CPEI message on Intel QuickPath
Interconnect, and so forth. IIO aborts all inbound accesses to this region. Outbound
accesses to this region is not explicitly decoded by IIO and are forwarded to
downstream subtractive decode port, if one exists, by virtue of subtractive decoding
else it is master aborted.
5.2.5.4
Processor Local CSR, On-die ROM, and Processor PSeg
This region accommodates processor’s local CSRs, on-die ROM, and PSeg. IIO will block
all inbound accesses from PCIe to this address region and return a completer abort
response. Outbound accesses to this address range are not part of the normal
programming model and IIO subtractively sends such accesses to the subtractive
decode port of the IIO, if one exists downstream (else Master Abort).
all inbound accesses from PCIe to this address region and return a completer abort
response. Outbound accesses to this address range are not part of the normal
programming model and IIO subtractively sends such accesses to the subtractive
decode port of the IIO, if one exists downstream (else Master Abort).
5.2.5.5
Legacy/HPET/TXT/TPM/Others
This region covers the High performance event timers, TXT registers, TPM region, and
so forth, in the PCH. All inbound/peer-to-peer accesses to this region are completer
aborted by IIO.
so forth, in the PCH. All inbound/peer-to-peer accesses to this region are completer
aborted by IIO.
Address Region
From
To
MMIOL
GMMIOL.Base
GMMIOL.Limit
Address Region
From
To
Misc
FE80_0000h
FE9F_FFFFh
Address Region
From
To
processor Local CSR and PSeg
FEB0_0000h
FEBF_FFFFh
Address Region
From
To
Legacy/HPET/TXT/TPM/Others
FED0_0000h
FEDF_FFFFh