Intel Xeon L3406 CM80616005010AA 사용자 설명서
제품 코드
CM80616005010AA
Datasheet, Volume 2
285
System Address Map
5.2.5.6
Local XAPIC
The processor Interrupt space is the address used to deliver interrupts to the
processor(s). Message Signaled Interrupts (MSI) from PCIe devices that target this
address are forwarded as SpcInt messages to the processor.
processor(s). Message Signaled Interrupts (MSI) from PCIe devices that target this
address are forwarded as SpcInt messages to the processor.
The processors may also use this region to send inter-processor interrupts (IPI) from
one processor to another. But, IIO is never a recipient of such an interrupt. Inbound
reads to this address are considered errors and are completer aborted by IIO.
Outbound accesses to this address are considered as errors, but IIO does not explicitly
check for this error condition but simply forwards the transaction subtractively to its
subtractive decode port, if one exists downstream.
one processor to another. But, IIO is never a recipient of such an interrupt. Inbound
reads to this address are considered errors and are completer aborted by IIO.
Outbound accesses to this address are considered as errors, but IIO does not explicitly
check for this error condition but simply forwards the transaction subtractively to its
subtractive decode port, if one exists downstream.
5.2.5.7
High BIOS Area
The top 2 MB (FFE0_0000h–FFFF_FFFFh) of the PCI Memory Address Range is reserved
for System BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the
system BIOS. The processor begins execution from the High BIOS after reset. This
region is mapped to DMI Interface so that the upper subset of this region aliases to 16-
MB to 256-KB range. The actual address space required for the BIOS is less than 2 MB,
but the minimum processor MTRR range for this region is 2 MB — so that full 2 MB
must be considered.
for System BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the
system BIOS. The processor begins execution from the High BIOS after reset. This
region is mapped to DMI Interface so that the upper subset of this region aliases to 16-
MB to 256-KB range. The actual address space required for the BIOS is less than 2 MB,
but the minimum processor MTRR range for this region is 2 MB — so that full 2 MB
must be considered.
5.2.5.8
INTA/Rsvd
This region accommodates IPF architecture-specific address regions. All inbound
accesses to this address region are completer aborted by the IIO. All outbound
accesses to this address region are subtractively sent to the subtractive decode port of
the IIO, if one exists downstream.
accesses to this address region are completer aborted by the IIO. All outbound
accesses to this address region are subtractively sent to the subtractive decode port of
the IIO, if one exists downstream.
5.2.5.9
Firmware
This ranges starts at FF00_0000h and ends at FFFF_FFFFh. It is used for
BIOS/Firmware. Outbound accesses within this range are forwarded to firmware hubs.
Refer to
BIOS/Firmware. Outbound accesses within this range are forwarded to firmware hubs.
Refer to
for firmware decoding details in IIO. During boot initialization,
IIO with firmware connected south of it will communicate this on all Intel QuickPath
Interconnect ports so that processor hardware can configure the path to firmware. IIO
does not support accesses to this address range inbound, that is, those inbound
transactions are aborted and a completer abort response is sent back.
Interconnect ports so that processor hardware can configure the path to firmware. IIO
does not support accesses to this address range inbound, that is, those inbound
transactions are aborted and a completer abort response is sent back.
Address Region
From
To
Local XAPIC
FEE0_0000h
FEEF_FFFFh
Address Region
From
To
IntA/Others
FEF0_0000h
FEFF_FFFFh
Address Region
From
To
HIGHBIO
FF00_0000h
FFFF_FFFFh