IBM powerpc 750gx 사용자 설명서
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_02.fm.(1.2)
March 27, 2006
March 27, 2006
Programming Model
Page 101 of 377
Integer Store Instructions
For integer store instructions, the contents of the source register (rS) are stored into the byte, half word, or
word in memory addressed by the EA. Many store instructions have an update form, in which rA is updated
with the EA. For these forms, the following rules apply:
word in memory addressed by the EA. Many store instructions have an update form, in which rA is updated
with the EA. For these forms, the following rules apply:
• If rA
≠
0, the effective address is placed into rA.
• If rS = rA, the contents of register rS are copied to the target memory element, and then the generated
EA is placed into rA (rS).
The PowerPC Architecture defines store with update instructions with rA = 0 as an invalid form. In addition, it
defines integer store instructions with the CR update option enabled (Rc field, bit 31, in the instruction
encoding = 1) to be an invalid form.
defines integer store instructions with the CR update option enabled (Rc field, bit 31, in the instruction
encoding = 1) to be an invalid form.
Table 2-19 summarizes the integer store instructions.
Integer Store Gathering
The 750GX performs store gathering for write-through accesses to nonguarded space or to cache-inhibited
stores to nonguarded space if the stores are 4 bytes and they are word-aligned. These stores are combined
in the load/store unit (LSU) to form a double word that is sent out on the 60x bus as a single-beat operation.
Stores are gathered only if successive, eligible stores are queued and pending. Store gathering takes place
regardless of address order or endian mode. The store-gathering feature is enabled by setting the HID0[SGE]
bit (bit 24).
stores to nonguarded space if the stores are 4 bytes and they are word-aligned. These stores are combined
in the load/store unit (LSU) to form a double word that is sent out on the 60x bus as a single-beat operation.
Stores are gathered only if successive, eligible stores are queued and pending. Store gathering takes place
regardless of address order or endian mode. The store-gathering feature is enabled by setting the HID0[SGE]
bit (bit 24).
Store gathering is not done for:
• Cacheable stores
• Stores to guarded cache-inhibited or write-through space
• Byte-reverse store
• Store Word Conditional Indexed (stwcx.) and External Control Out Word Indexed (ecowx) accesses
• Floating-point stores
• Stores to guarded cache-inhibited or write-through space
• Byte-reverse store
• Store Word Conditional Indexed (stwcx.) and External Control Out Word Indexed (ecowx) accesses
• Floating-point stores
Table 2-19. Integer Store Instructions
Name
Mnemonic
Syntax
Store Byte
stb
rS,d(rA)
Store Byte Indexed
stbx
rS,rA,rB
Store Byte with Update
stbu
rS,d(rA)
Store Byte with Update Indexed
stbux
rS,rA,rB
Store Half Word
sth
rS,d(rA)
Store Half Word Indexed
sthx
rS,rA,rB
Store Half Word with Update sthu
rS,d(rA)
Store Half Word with Update Indexed
sthux
rS,rA,rB
Store Word
stw
rS,d(rA)
Store Word Indexed
stwx
rS,rA,rB
Store Word with Update
stwu
rS,d(rA)
Store Word with Update Indexed
stwux
rS,rA,rB