IBM powerpc 750gx 사용자 설명서
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Signal Descriptions
Page 274 of 377
gx_07.fm.(1.2)
March 27, 2006
7.2.11.4 Time Base Enable (TBEN)—Input
7.2.11.5 TLB Invalidate Synchronize (TLBISYNC)—Input
The TLB Invalidate Synchronize (TLBISYNC) signal is an input-only signal.
7.2.12 Processor Mode Selection Signals
Table 7-6 summarizes the processor mode select signals of the 750GX. The mode select signals establish
the operating modes of the processor after reset (for example, 32-bit or 64-bit data mode or DRTRY mode).
Mode select signals are sampled at the rising transition of HRESET.
the operating modes of the processor after reset (for example, 32-bit or 64-bit data mode or DRTRY mode).
Mode select signals are sampled at the rising transition of HRESET.
State
Asserted
Indicates that the time base and decrementer should continue clocking. This
signal is essentially a “count enable” control for the time base and decre-
menter counter.
signal is essentially a “count enable” control for the time base and decre-
menter counter.
Negated
Indicates that the time base and decrementer should stop clocking.
Timing
Assertion/
Negation
Negation
May occur on any cycle. The sampling of this signal is synchronous with
SYSCLK.
SYSCLK.
State
Asserted
Prevents execution of a tlbsync instruction from completing.
Negated
Enables execution of a tlbsync to complete.
Timing
Assertion/
Negation
Negation
Might occur on any cycle.
Start-Up
See Table 7-6, Summary of Mode Select Signals, on page 274 for a descrip-
tion of the start-up function.
tion of the start-up function.
Table 7-6. Summary of Mode Select Signals
Pin
Description
Pin state at HRESET transition
'0'
'1'
DRTRY
Selects DRTRY mode.
No-DRTRY mode
DRTRY mode
QACK
QACK selects normal or full cycle precharge
on ABB, DBB, and ARTRY.
on ABB, DBB, and ARTRY.
Full cycle precharge
Normal precharge
TLBISYNC
TLBISYNC selects 32-bit or 64-bit bus mode.
32-bit mode
64-bit mode
DBWO
Factory usage mode only. Must be tied high at
HRESET transition.
HRESET transition.
N/A
Required
DBDIS
Factory usage mode only. Must be tied high at
HRESET transition.
HRESET transition.
N/A
Required
L2_TSTCLK
Factory usage mode only. Must be tied high at
HRESET transition.
HRESET transition.
N/A
Required