IBM powerpc 750gx 사용자 설명서
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Bus Interface Operation
Page 290 of 377
gx_08.fm.(1.2)
March 27, 2006
8.2.2.2 Speculative Loads and Conditional Branches
Loads that are dispatched before a preceding conditional branch is resolved are speculative. Mispredicted
branches cause the speculative loads to be canceled. Normally, the cancellation is confined to the load/store
unit, and no additional cycles are wasted. However, this is not the case when MuM is enabled. The specula-
tive loads might be MuM requests that have started on the 60x bus. All outstanding MuM requests must
complete, since there is no way to cancel them once they are started on the 60x bus. The load/store unit is
now stalled until all outstanding loads have completed. The data cache is not reloaded for any MuM request
that is canceled. However, the MuM reload is loaded into the L2 cache if enabled.
branches cause the speculative loads to be canceled. Normally, the cancellation is confined to the load/store
unit, and no additional cycles are wasted. However, this is not the case when MuM is enabled. The specula-
tive loads might be MuM requests that have started on the 60x bus. All outstanding MuM requests must
complete, since there is no way to cancel them once they are started on the 60x bus. The load/store unit is
now stalled until all outstanding loads have completed. The data cache is not reloaded for any MuM request
that is canceled. However, the MuM reload is loaded into the L2 cache if enabled.
8.3 Address-Bus Tenure
This section describes the three phases of the address tenure—address-bus arbitration, address transfer,
and address termination.
and address termination.
8.3.1 Address-Bus Arbitration
When the 750GX needs access to the external bus and it is not parked (BG is negated), it asserts the bus
request (BR) signal until it is granted mastership of the bus and the bus is available (see Figure 8-6). The
external arbiter must grant master-elect status to the potential master by asserting the bus grant (BG) signal.
The 750GX requesting the bus determines that the bus is available when the ABB input is negated. When the
address bus is not busy (ABB input is negated), BG is asserted and the address retry (ARTRY) input is
negated. This is referred to as a qualified bus grant. The potential master assumes address-bus mastership
by asserting ABB when it receives a qualified bus grant.
request (BR) signal until it is granted mastership of the bus and the bus is available (see Figure 8-6). The
external arbiter must grant master-elect status to the potential master by asserting the bus grant (BG) signal.
The 750GX requesting the bus determines that the bus is available when the ABB input is negated. When the
address bus is not busy (ABB input is negated), BG is asserted and the address retry (ARTRY) input is
negated. This is referred to as a qualified bus grant. The potential master assumes address-bus mastership
by asserting ABB when it receives a qualified bus grant.
Figure 8-6. Address-Bus Arbitration
-1
0
1
need_bus
BR
bg
abb
artry
qual BG
ABB
Logical Bus Clock