IBM powerpc 750gx 사용자 설명서
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Bus Interface Operation
Page 300 of 377
gx_08.fm.(1.2)
March 27, 2006
8.3.2.5 Alignment of External Control Instructions
The size of the data transfer associated with the eciwx and ecowx instructions is always 4 bytes. If the eciwx
or ecowx instruction is misaligned and crosses any word boundary, the 750GX will generate an alignment
exception.
or ecowx instruction is misaligned and crosses any word boundary, the 750GX will generate an alignment
exception.
8.3.3 Address Transfer Termination
The address tenure of a bus operation is terminated when completed with the assertion of AACK, or retried
with the assertion of ARTRY. The 750GX does not terminate the address transfer until the AACK input is
asserted. Therefore, the system can extend the address transfer phase by delaying the assertion of AACK to
the 750GX. The assertion of AACK can be as early as the bus clock cycle following TS (see Figure 8-9 on
page 301), which allows a minimum address tenure of two bus cycles. As shown in Figure 8-9, these signals
are asserted for one bus clock cycle, tristated for half of the next bus clock cycle, driven high until the
following bus cycle, and finally tristated. Note that AACK must be asserted for only one bus clock cycle.
with the assertion of ARTRY. The 750GX does not terminate the address transfer until the AACK input is
asserted. Therefore, the system can extend the address transfer phase by delaying the assertion of AACK to
the 750GX. The assertion of AACK can be as early as the bus clock cycle following TS (see Figure 8-9 on
page 301), which allows a minimum address tenure of two bus cycles. As shown in Figure 8-9, these signals
are asserted for one bus clock cycle, tristated for half of the next bus clock cycle, driven high until the
following bus cycle, and finally tristated. Note that AACK must be asserted for only one bus clock cycle.
The address transfer can be terminated with the requirement to retry if ARTRY is asserted anytime during the
address tenure and through the cycle following AACK. The assertion causes the entire transaction (address
and data tenure) to be rerun. As a snooping device, the 750GX asserts ARTRY for a snooped transaction that
hits modified data in the data cache that must be written back to memory, or if the snooped transaction could
not be serviced. As a bus master, the 750GX responds to an assertion of ARTRY by canceling the bus trans-
action and rerequesting the bus. Note that after recognizing an assertion of ARTRY and canceling the trans-
action in progress, the 750GX is not guaranteed to run the same transaction the next time it is granted the
bus due to internal reordering of load-and-store operations.
address tenure and through the cycle following AACK. The assertion causes the entire transaction (address
and data tenure) to be rerun. As a snooping device, the 750GX asserts ARTRY for a snooped transaction that
hits modified data in the data cache that must be written back to memory, or if the snooped transaction could
not be serviced. As a bus master, the 750GX responds to an assertion of ARTRY by canceling the bus trans-
action and rerequesting the bus. Note that after recognizing an assertion of ARTRY and canceling the trans-
action in progress, the 750GX is not guaranteed to run the same transaction the next time it is granted the
bus due to internal reordering of load-and-store operations.
If an address retry is required, the ARTRY response will be asserted by a bus snooping device as early as the
second cycle after the assertion of TS. Once asserted, ARTRY must remain asserted through the cycle after
the assertion of AACK. The assertion of ARTRY during the cycle after the assertion of AACK is referred to as
a qualified ARTRY. An earlier assertion of ARTRY during the address tenure is referred to as an early
ARTRY.
second cycle after the assertion of TS. Once asserted, ARTRY must remain asserted through the cycle after
the assertion of AACK. The assertion of ARTRY during the cycle after the assertion of AACK is referred to as
a qualified ARTRY. An earlier assertion of ARTRY during the address tenure is referred to as an early
ARTRY.
As a bus master, the 750GX recognizes either an early or qualified ARTRY and prevents the data tenure
associated with the retried address tenure. If the data tenure has already begun, the 750GX cancels and
terminates the data tenure immediately even if the burst data has been received. If the assertion of ARTRY is
received up to or on the bus cycle following the first (or only) assertion of TA for the data tenure, the 750GX
ignores the first data beat, and if it is a load operation, does not forward data internally to the cache and
execution units. If ARTRY is asserted after the first (or only) assertion of TA, improper operation of the bus
interface can result.
associated with the retried address tenure. If the data tenure has already begun, the 750GX cancels and
terminates the data tenure immediately even if the burst data has been received. If the assertion of ARTRY is
received up to or on the bus cycle following the first (or only) assertion of TA for the data tenure, the 750GX
ignores the first data beat, and if it is a load operation, does not forward data internally to the cache and
execution units. If ARTRY is asserted after the first (or only) assertion of TA, improper operation of the bus
interface can result.
During the clock of a qualified ARTRY, the 750GX also determines if it should negate BR and ignore BG on
the following cycle. On the following cycle, only the snooping master that asserted ARTRY and needs to
perform a snoop copy-back operation is allowed to assert BR. This guarantees the snooping master an
opportunity to request and be granted the bus before the just-retried master can restart its transaction. Note
that a nonclocked bus arbiter might detect the assertion of address-bus request by the bus master that
asserted ARTRY, and return a qualified bus grant one cycle earlier than shown in Figure 8-9.
the following cycle. On the following cycle, only the snooping master that asserted ARTRY and needs to
perform a snoop copy-back operation is allowed to assert BR. This guarantees the snooping master an
opportunity to request and be granted the bus before the just-retried master can restart its transaction. Note
that a nonclocked bus arbiter might detect the assertion of address-bus request by the bus master that
asserted ARTRY, and return a qualified bus grant one cycle earlier than shown in Figure 8-9.
Note that if the 750GX asserts ARTRY due to a snoop operation, and asserts BR in the bus cycle following
ARTRY in order to perform a snoop push to memory, the 750GX might not be able to accept a BG until
several bus cycles later. (The delay in responding to the assertion of BG only occurs during snoop pushes
from the L2 cache.) The bus arbiter should keep BG asserted until it detects BR negated or TS asserted from
the 750GX, which indicates that the snoop copy-back has begun. The system should ensure that no other
ARTRY in order to perform a snoop push to memory, the 750GX might not be able to accept a BG until
several bus cycles later. (The delay in responding to the assertion of BG only occurs during snoop pushes
from the L2 cache.) The bus arbiter should keep BG asserted until it detects BR negated or TS asserted from
the 750GX, which indicates that the snoop copy-back has begun. The system should ensure that no other