IBM powerpc 750gx 사용자 설명서
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Bus Interface Operation
Page 302 of 377
gx_08.fm.(1.2)
March 27, 2006
A qualified data-bus grant can be expressed as the following:
QDBG = DBG asserted while DBB, DRTRY, and ARTRY (associated with the data-bus operation) are
negated.
negated.
When a data tenure overlaps with its associated address tenure, a qualified ARTRY assertion coincident with
a data-bus grant signal does not result in data-bus mastership (DBB is not asserted). Otherwise, the 750GX
always asserts DBB on the bus clock cycle after recognition of a qualified data-bus grant. Since the 750GX
can pipeline transactions, there might be an outstanding data-bus transaction when a new address transac-
tion is retried. In this case, the 750GX becomes the data-bus master to complete the outstanding transaction.
a data-bus grant signal does not result in data-bus mastership (DBB is not asserted). Otherwise, the 750GX
always asserts DBB on the bus clock cycle after recognition of a qualified data-bus grant. Since the 750GX
can pipeline transactions, there might be an outstanding data-bus transaction when a new address transac-
tion is retried. In this case, the 750GX becomes the data-bus master to complete the outstanding transaction.
8.4.1.1 Using the DBB Signal
The DBB signal should be connected between masters if data tenure scheduling is left to the masters.
Optionally, the memory system can control data tenure scheduling directly with DBG. However, it is possible
to ignore the DBB signal in the system if the DBB input is not used as the final data-bus allocation control
between data-bus masters, and if the memory system can track the start and end of the data tenure. If DBB is
not used to signal the end of a data tenure, DBG is only asserted to the next bus master the cycle before the
cycle that the next bus master might actually begin its data tenure, rather than asserting it earlier (usually
during another master’s data tenure) and allowing the negation of DBB to be the final gating signal for a qual-
ified data-bus grant. Even if DBB is ignored in the system, the 750GX always recognizes its own assertion of
DBB, and requires one cycle after data tenure completion to negate its own DBB before recognizing a quali-
fied data-bus grant for another data tenure. If DBB is ignored in the system, it must still be connected to a
pull-up resistor on the 750GX to ensure proper operation.
Optionally, the memory system can control data tenure scheduling directly with DBG. However, it is possible
to ignore the DBB signal in the system if the DBB input is not used as the final data-bus allocation control
between data-bus masters, and if the memory system can track the start and end of the data tenure. If DBB is
not used to signal the end of a data tenure, DBG is only asserted to the next bus master the cycle before the
cycle that the next bus master might actually begin its data tenure, rather than asserting it earlier (usually
during another master’s data tenure) and allowing the negation of DBB to be the final gating signal for a qual-
ified data-bus grant. Even if DBB is ignored in the system, the 750GX always recognizes its own assertion of
DBB, and requires one cycle after data tenure completion to negate its own DBB before recognizing a quali-
fied data-bus grant for another data tenure. If DBB is ignored in the system, it must still be connected to a
pull-up resistor on the 750GX to ensure proper operation.
Figure 8-10. Data-Bus Arbitration
0
1
2
3
TS
dbg
dbb
drtry
qual DBG
DBB