IBM powerpc 750gx 사용자 설명서
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Programming Model
Page 62 of 377
gx_02.fm.(1.2)
March 27, 2006
Register 1 (SRR1)” in Chapter 2, “PowerPC Register Set” of the PowerPC Microprocessor Fam-
ily: The Programming Environments Manual for more information.
ily: The Programming Environments Manual for more information.
Note: When a machine-check exception occurs, the 750GX sets one or more error bits in SRR1.
Table 2-2 describes SRR1 bits 750GX implements that are not required by the PowerPC Archi-
tecture.
Table 2-2 describes SRR1 bits 750GX implements that are not required by the PowerPC Archi-
tecture.
– Miscellaneous registers
• Time Base (TB). The TB is a 64-bit structure provided for maintaining the time of day and operat-
ing interval timers. The TB consists of two 32-bit registers—Time Base Upper (TBU) and Time
Base Lower (TBL). The Time Base Registers can be written to only by supervisor-level software,
but can be read by both user- and supervisor-level software. See “Time Base Facility (TB)—
OEA” in Chapter 2, “PowerPC Register Set” of the PowerPC Microprocessor Family: The Pro-
gramming Environments Manual for more information.
Base Lower (TBL). The Time Base Registers can be written to only by supervisor-level software,
but can be read by both user- and supervisor-level software. See “Time Base Facility (TB)—
OEA” in Chapter 2, “PowerPC Register Set” of the PowerPC Microprocessor Family: The Pro-
gramming Environments Manual for more information.
• Decrementer Register (DEC). This register is a 32-bit decrementing counter that provides a
mechanism for causing a decrementer exception after a programmable delay; the frequency is a
subdivision of the processor clock. See “Decrementer Register (DEC)” in Chapter 2, “PowerPC
Register Set” of the PowerPC Microprocessor Family: The Programming Environments Manual
for more information.
subdivision of the processor clock. See “Decrementer Register (DEC)” in Chapter 2, “PowerPC
Register Set” of the PowerPC Microprocessor Family: The Programming Environments Manual
for more information.
Note: In the 750GX, the Decrementer Register is decremented and the time base is incre-
mented at a speed that is one-fourth the speed of the bus clock.
mented at a speed that is one-fourth the speed of the bus clock.
• Data Address Breakpoint Register (DABR)—This optional register is used to cause a breakpoint
exception if a specified data address is encountered. See “Data Address Breakpoint Register
(DABR)” in Chapter 2, “PowerPC Register Set” of the PowerPC Microprocessor Family: The Pro-
gramming Environments Manual.
(DABR)” in Chapter 2, “PowerPC Register Set” of the PowerPC Microprocessor Family: The Pro-
gramming Environments Manual.
• External Access Register (EAR). This optional register is used in conjunction with the External
Control In Word Indexed (eciwx) and External Control Out Word Indexed (ecowx) instructions.
Note that the EAR and the eciwx and ecowx instructions are optional in the PowerPC Architec-
ture and might not be supported in all PowerPC processors that implement the OEA. See “Exter-
nal Access Register (EAR)” in Chapter 2, “PowerPC Register Set” of the PowerPC
Microprocessor Family: The Programming Environments Manual for more information.
Note that the EAR and the eciwx and ecowx instructions are optional in the PowerPC Architec-
ture and might not be supported in all PowerPC processors that implement the OEA. See “Exter-
nal Access Register (EAR)” in Chapter 2, “PowerPC Register Set” of the PowerPC
Microprocessor Family: The Programming Environments Manual for more information.
• 750GX-specific registers—The PowerPC Architecture allows implementation-specific SPRs. Those
described below are incorporated in the 750GX. Note that, in the 750GX, these registers are all supervi-
sor-level registers.
sor-level registers.
– Instruction Address Breakpoint Register (IABR)—This register can be used to cause a breakpoint
exception if a specified instruction address is encountered.
Table 2-2. Additional SRR1 Bits
Bit
Name
Description
4
CP
Internal cache parity error.
11
L2DBERR
Set by a double-bit error checking and correction (ECC) error in the L2.
12
MCpin
Set by the assertion of the machine-check interrupt (MCP).
13
TEA
Set by a transfer error acknowledge (TEA) assertion on the 60x bus.
14
DP
Set by a data-parity error on the 60x bus.
15
AP
Set by an address-parity error on the 60x bus.