IBM powerpc 750gx 사용자 설명서
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Programming Model
Page 74 of 377
gx_02.fm.(1.2)
March 27, 2006
Monitor Mode Control Register 1 (MMCR1)
The Monitor Mode Control Register 1 (MMCR1) functions as an event selector for Performance-Monitor
Counter Registers 3 and 4 (PMC3 and PMC4). Corresponding events to the MMCR1 bits are described in
Performance-Monitor Counter Registers (PMCn).
Counter Registers 3 and 4 (PMC3 and PMC4). Corresponding events to the MMCR1 bits are described in
Performance-Monitor Counter Registers (PMCn).
MMCR1 can be accessed with mtspr and mfspr using SPR 956. User-level software can read the contents
of MMCR1 by issuing an mfspr instruction to UMMCR1, described in the following section.
of MMCR1 by issuing an mfspr instruction to UMMCR1, described in the following section.
User Monitor Mode Control Register 1 (UMMCR1)
The contents of MMCR1 are reflected to UMMCR1, which can be read by user-level software. MMCR1 can
be accessed with mfspr using SPR 940.
be accessed with mfspr using SPR 940.
Performance-Monitor Counter Registers (PMCn)
PMC1–PMC4 are 32-bit counters that can be programmed to generate interrupt signals when they overflow.
Counters are considered to overflow when the high-order bit (the sign bit) becomes set; that is, they reach the
value 2147483648 (0x8000_0000). However, an interrupt is not signaled unless both PMCn[INTCONTROL]
and MMCR0[ENINT] are also set.
Counters are considered to overflow when the high-order bit (the sign bit) becomes set; that is, they reach the
value 2147483648 (0x8000_0000). However, an interrupt is not signaled unless both PMCn[INTCONTROL]
and MMCR0[ENINT] are also set.
Note: The interrupts can be masked by clearing MSR[EE]; the interrupt signal condition can occur with
MSR[EE] cleared, but the exception is not taken until EE is set. Setting MMCR0[DISCOUNT] forces counters
to stop counting when a counter interrupt occurs.
MSR[EE] cleared, but the exception is not taken until EE is set. Setting MMCR0[DISCOUNT] forces counters
to stop counting when a counter interrupt occurs.
Software is expected to use mtspr to set PMC explicitly to nonoverflow values. If software sets an overflow
value, an erroneous exception might occur. For example, if both PMCn[INTCONTROL] and MMCR0[ENINT]
are set and mtspr loads an overflow value, an interrupt signal will be generated without any event counting
having taken place.
value, an erroneous exception might occur. For example, if both PMCn[INTCONTROL] and MMCR0[ENINT]
are set and mtspr loads an overflow value, an interrupt signal will be generated without any event counting
having taken place.
The event to be monitored by PMC1 can be chosen by setting MMCR0[19:25]. The event to be monitored by
PMC2 can be chosen by setting MMCR0[26:31]. The event to be monitored by PMC3 can be chosen by
setting MMCR1[0:4]. The event to be monitored by PMC4 can be chosen by setting MMCR1[5:9]. The
selected events are counted beginning when MMCR0 is set until either MMCR0 is reset or a performance-
monitor interrupt is generated.
PMC2 can be chosen by setting MMCR0[26:31]. The event to be monitored by PMC3 can be chosen by
setting MMCR1[0:4]. The event to be monitored by PMC4 can be chosen by setting MMCR1[5:9]. The
selected events are counted beginning when MMCR0 is set until either MMCR0 is reset or a performance-
monitor interrupt is generated.
PMC3SELECT
PMC4SELECT
Reserved
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Bits
Field Name
Description
0:4
PMC3SELECT
PMC3 input selector. Thirty-two events selectable. See Performance-Monitor Counter
Registers (PMCn) on page 74 for defined selections.
Registers (PMCn) on page 74 for defined selections.
5:9
PMC4SELECT
PMC4 input selector. Thirty-two events selectable. See Performance-Monitor Counter
Registers (PMCn) on page 74 for defined selections.
Registers (PMCn) on page 74 for defined selections.
10:31
Reserved
Reserved.