IBM powerpc 750gx 사용자 설명서
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Programming Model
Page 96 of 377
gx_02.fm.(1.2)
March 27, 2006
Double-precision arithmetic instructions, except those involving multiplication (fmul, fmadd, fmsub, fnmadd,
fnmsub) execute with the same latency as their single-precision equivalents. For additional details on
floating-point performance, see Chapter 6, Instruction Timing, on page 209.
fnmsub) execute with the same latency as their single-precision equivalents. For additional details on
floating-point performance, see Chapter 6, Instruction Timing, on page 209.
Floating-Point Multiply/Add Instructions
These instructions combine multiply and add operations without an intermediate rounding operation. The
floating-point multiply/add instructions are summarized in Table 2-13.
floating-point multiply/add instructions are summarized in Table 2-13.
Floating-Point Rounding and Conversion Instructions
The Floating Round to Single-Precision (frsp) instruction is used to truncate a 64-bit double-precision number
to a 32-bit single-precision floating-point number. The floating-point convert instructions convert a 64-bit
double-precision floating-point number to a 32-bit signed integer number.
to a 32-bit single-precision floating-point number. The floating-point convert instructions convert a 64-bit
double-precision floating-point number to a 32-bit signed integer number.
Table 2-12. Floating-Point Arithmetic Instructions
Name
Mnemonic
Syntax
Floating Add (Double-Precision)
fadd (fadd.)
frD,frA,frB
Floating Add Single
fadds (fadds.)
frD,frA,frB
Floating Subtract (Double-Precision)
fsub (fsub.)
frD,frA,frB
Floating Subtract Single
fsubs (fsubs.)
frD,frA,frB
Floating Multiply (Double-Precision)
fmul (fmul.)
frD,frA,frC
Floating Multiply Single
fmuls (fmuls.)
frD,frA,frC
Floating Divide (Double-Precision)
fdiv (fdiv.)
frD,frA,frB
Floating Divide Single
fdivs (fdivs.)
frD,frA,frB
Floating Reciprocal Estimate Single
fres (fres.)
frD,frB
Floating Reciprocal Square Root Estimate
frsqrte (frsqrte.)
frD,frB
Floating Select
fsel (fsel.)
frD,frA,frC,frB
1.
The fres, frsqrte, and fsel instructions are optional in the PowerPC Architecture.
Table 2-13. Floating-Point Multiply/Add Instructions
Name
Mnemonic
Syntax
Floating Multiply/Add (Double-Precision)
fmadd (fmadd.)
frD,frA,frC,frB
Floating Multiply/Add Single
fmadds (fmadds.)
frD,frA,frC,frB
Floating Multiply/Subtract (Double-Precision)
fmsub (fmsub.)
frD,frA,frC,frB
Floating Multiply/Subtract Single
fmsubs (fmsubs.)
frD,frA,frC,frB
Floating Negative Multiply/Add (Double-Precision)
fnmadd (fnmadd.)
frD,frA,frC,frB
Floating Negative Multiply/Add Single
fnmadds (fnmadds.)
frD,frA,frC,frB
Floating Negative Multiply/Subtract (Double-Preci-
sion)
sion)
fnmsub (fnmsub.)
frD,frA,frC,frB
Floating Negative Multiply/Subtract Single
fnmsubs (fnmsubs.)
frD,frA,frC,frB