dresden elektronik ingenieurtechnik gmbh MEGA22M00 사용자 설명서
User Manual
Version 1.1c
2013-07-01
Version 1.1c
2013-07-01
OEM
radio modules deRFmega
www.dresden-elektronik.de
Page 27 of 52
7.2.1. External front-end and antenna diversity control
The radio module deRFmega128-22M10 offers the possibility to control external front-end
components and to support antenna diversity. Table 7-3 and Table 7-4 show the logic values
of the control signals.
components and to support antenna diversity. Table 7-3 and Table 7-4 show the logic values
of the control signals.
A logic ‘0’ is specified with a voltage level of 0 V to 0.3 V. A logic ‘1’ is
specified with a value of VCC - 0.3 V to 3.6 V.
An application circuit is shown in Section 10.5.
Antenna Diversity
The antenna diversity algorithm is enabled with setting bit ANT_DIV_EN=1 in the ANT_DIV
register. The external control of RF switches must be enabled by bit ANT_EXT_SW_EN of
the same register. This action will configure the pins DIG1 and DIG2 as outputs. Both pins
are used to feed the RF switch signal and its inverse to the differential inputs of the RF
switch. Please refer to ATmega128RFA1 datasheet [1] to get information to all register
settings.
An application circuit is shown in Section 10.5.
Antenna Diversity
The antenna diversity algorithm is enabled with setting bit ANT_DIV_EN=1 in the ANT_DIV
register. The external control of RF switches must be enabled by bit ANT_EXT_SW_EN of
the same register. This action will configure the pins DIG1 and DIG2 as outputs. Both pins
are used to feed the RF switch signal and its inverse to the differential inputs of the RF
switch. Please refer to ATmega128RFA1 datasheet [1] to get information to all register
settings.
Table 7-3: Antenna diversity control
Mode description
PG1/DIG1
PF2/DIG2
TRX off
Sleep mode
Sleep mode
Disable register bit ANT_EXT_SW_EN and set port
pins DIG1 and DIG2 to output low via I/O port control
registers. This action could reduce the power
consumption of an external RF switch.
pins DIG1 and DIG2 to output low via I/O port control
registers. This action could reduce the power
consumption of an external RF switch.
ANT0
1
0
ANT1
0
1
Front-End
The control of front-end components can be realized with the signals DIG3 and DIG4. The
function will be enabled with bit PA_EXT_EN of register TRX_CTRL_1 which configures both
pins as outputs. While transmission is turned off DIG3 is set to ‘0’ and DIG4 is set to ‘1’.
When the transceiver starts transmission the polarity will be changed. Both pins can be used
to control PA, LNA and RF switches. Please refer to ATmega128RFA1 datasheet [1] to get
information to all register settings.
Table 7-4: Front-end control
PG0/DIG3
PF3/DIG4
TRX off
Sleep mode
Sleep mode
Disable register bit PA_EXT_EN and set port pins
DIG3 and DIG4 to output low via I/O port control
registers. This action may reduce the power
consumption of external front-end devices.
DIG3 and DIG4 to output low via I/O port control
registers. This action may reduce the power
consumption of external front-end devices.
TRX off
0
1
TRX on
1
0
Sleep mode
To optimize the power consumption of external front-end components, it is possible to use a
dedicated GPIO to set the PA into sleep mode, if applicable or to switch an additionally
MOSFET, which supplies the PA.