Gemalto M2M GmbH EHS6-A 사용자 설명서
Cinterion
®
EHS6-A Hardware Interface Overview
Page 18 of 41
2.1 Application Interface
22
EHS6-A_HIO_v02.770
2014-08-13
Confidential / Preliminary
GPIO17
TXD1
MISO
HOST_ACTIVE
GPIO18
RTS1
CP_WAKEUP
GPIO19
CTS1
SPI_CS
SUSPEND
GPIO20
TXDDAI
GPIO21
RXDDAI
GPIO22
TFSDAI
GPIO23
SCLK
GPIO24
RING0
After startup, the above mentioned alternative GPIO line assignments can be configured using
AT commands (see
[1]
). The configuration is non-volatile and available after module restart.
2.1.8
I
2
C Interface
I
2
C is a serial, 8-bit oriented data transfer bus for bit rates up to 400kbps in Fast mode. It
consists of two lines, the serial data line I2CDAT and the serial clock line I2CCLK. The module
acts as a single master device, e.g. the clock I2CCLK is driven by the module. I2CDAT is a bi-
directional line. Each device connected to the bus is software addressable by a unique 7-bit
address, and simple master/slave relationships exist at all times. The module operates as
mastertransmitter or as master-receiver. The customer application transmits or receives data
only on request of the module.
acts as a single master device, e.g. the clock I2CCLK is driven by the module. I2CDAT is a bi-
directional line. Each device connected to the bus is software addressable by a unique 7-bit
address, and simple master/slave relationships exist at all times. The module operates as
mastertransmitter or as master-receiver. The customer application transmits or receives data
only on request of the module.
The I
2
C interface can be powered via the V180 line of EHS6-A. If connected to the V180 line,
the I
2
C interface will properly shut down when the module enters the Power Down mode.
Note: Good care should be taken when creating the PCB layout of the host application: The
traces of I2CCLK and I2CDAT should be equal in length and as short as possible.
2.1.9
SPI Interface
Four EHS6-A GPIO interface lines can be configured as Serial Peripheral Interface (SPI). The
SPI is a synchronous serial interface for control and data transfer between EHS6-A and the
external application. Only one application can be connected to the SPI and the interface
supports only master mode. The transmission rates are up to 6.5Mbit/s. The SPI interface
comprises the two data lines MOSI and MISO, the clock line SPI_CLK a well as the chip select
line SPI_CS.
external application. Only one application can be connected to the SPI and the interface
supports only master mode. The transmission rates are up to 6.5Mbit/s. The SPI interface
comprises the two data lines MOSI and MISO, the clock line SPI_CLK a well as the chip select
line SPI_CS.
2.1.10 HSIC Interface
The (USB) High Speed Inter Chip Interface can be used between the module and an external
application processor and is compliant to the High Speed USB 2.0 interface with 480Mbit/s.
The maximum distance between module processor and external application processor should
not exceed 100mm.
The maximum distance between module processor and external application processor should
not exceed 100mm.