Fujifilm Xeon 5110 S26361-F3250-L160 데이터 시트

Dual-Core Intel

® 

Xeon

® 

Processor 5100 Series Datasheet

69

INIT#

I

INIT# (Initialization), when asserted, resets integer registers inside all processors 

without affecting their internal caches or floating-point registers. Each processor then 

begins execution at the power-on Reset vector configured during power-on 

configuration. The processor continues to handle snoop requests during INIT# 

assertion. INIT# is an asynchronous signal and must connect the appropriate pins of 

all processor FSB agents.

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LINT[1:0]

I

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all FSB agents. 

When the APIC functionality is disabled, the LINT0/INTR signal becomes INTR, a 

maskable interrupt request signal, and LINT1/NMI becomes NMI, a nonmaskable 

interrupt. INTR and NMI are backward compatible with the signals of those names on 

the Pentium

®

 processor. Both signals are asynchronous.

These signals must be software configured via BIOS programming of the APIC register 

space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by 

default after Reset, operation of these pins as LINT[1:0] is the default configuration.

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LL_ID[1:0]

O

The LL_ID[1:0] signals are used to select the correct loadline slope for the processor. 

These signals are not connected to the processor die. A logic 0 is pulled to ground and 

a logic 1 is a no-connect on the Dual-Core Intel

® 

Xeon

® 

Processor 5100 Series  

package.

LOCK#

I/O

LOCK# indicates to the system that a transaction must occur atomically. This signal 

must connect the appropriate pins of all processor FSB agents. For a locked sequence 

of transactions, LOCK# is asserted from the beginning of the first transaction to the 

end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the processor 

FSB, it will wait until it observes LOCK# deasserted. This enables symmetric agents to 

retain ownership of the processor FSB throughout the bus locked operation and 

ensure the atomicity of lock.

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MCERR#

I/O

MCERR# (Machine Check Error) is asserted to indicate an unrecoverable 
error without a bus protocol violation. It may be driven by all processor 
FSB agents.
MCERR# assertion conditions are configurable at a system level. Assertion 
options are defined by the following options:

• Enabled or disabled.
• Asserted, if configured, for internal errors along with IERR#.
• Asserted, if configured, by the request initiator of a bus transaction after it 

observes an error.

• Asserted by any bus agent when it observes an error in a bus transaction.

For more details regarding machine check architecture, refer to the IA-32 Software 

Developer’s Manual, Volume 3: System Programming Guide.

MS_ID[1:0]

O

These signals are provided to indicate the Market Segment for the processor and may 

be used for future processor compatibility or for keying. These signals are not 

connected to the processor die. A logic 0 is pulled to ground and a logic 1 is a no-

connect on the Dual-Core Intel

® 

Xeon

® 

Processor 5100 Series  package.

PECI

I/O

PECI is a proprietary one-wire bus interface that provides a communication channel 

between Intel processor and chipset components to external thermal monitoring 

devices. See 

 for more on the PECI interface.

PROCHOT#

O

PROCHOT# (Processor Hot) will go active when the processor’s temperature 

monitoring sensor detects that the processor has reached its maximum safe operating 

temperature. This indicates that the Thermal Control Circuit (TCC) has been 

activated, if enabled. The TCC will remain active until shortly after the processor 

deasserts PROCHOT#. See 

 for more details.

PWRGOOD

I

PWRGOOD (Power Good) is an input. The processor requires this signal to be a clean 

indication that all processor clocks and power supplies are stable and within their 

specifications. “Clean” implies that the signal will remain low (capable of sinking 

leakage current), without glitches, from the time that the power supplies are turned 

on until they come within specification. The signal must then transition monotonically 

to a high state. PWRGOOD can be driven inactive at any time, but clocks and power 

must again be stable before a subsequent rising edge of PWRGOOD. It must also 

meet the minimum pulse width specification in 

, and be followed by a 1-

10 ms RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect internal 

circuits against voltage sequencing issues. It should be driven high throughout 

boundary scan operation.

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