Microchip Technology MCU PIC10F322T-I/OT SOT-23-6 MCP PIC10F322T-I/OT 데이터 시트

DS41585A-page 134

 2011 Microchip Technology Inc.

When the Accumulator overflows, the NCOx Interrupt
Flag bit, NCOxIF, of the PIR1 register is set. To enable
this interrupt event, the following bits must be set:
• NxEN bit of the NCOxCON register
• NCOxIE bit of the PIE1 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt must be cleared by software by clearing
the NCOxIF bit in the Interrupt Service Routine.

All of the NCOx registers are cleared to zero as the
result of a Reset.

The NCO module operates independently from the
system clock and will continue to run during Sleep,
provided that the clock source selected remains active.
The HFINTOSC remains active during Sleep when the
NCO module is enabled and the HFINTOSC is
selected as the clock source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and the NCO clock
source, when the NCO is enabled, the CPU will go idle
during Sleep, but the NCO will continue to operate and
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.