Texas Instruments IC FLPT TMS320C28346ZFET PBGA-256 TID TMS320C28346ZFET 데이터 시트
제품 코드
TMS320C28346ZFET
SPRS516D – MARCH 2009 – REVISED AUGUST 2012
Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these
blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these
blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to
different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause
problems in certain peripheral applications where the user expected the write to occur first (as written).
The C28x CPU supports a block protection mode where a region of memory can be protected so as to
make sure that operations occur as written (the penalty is extra cycles are added to align the operations).
This mode is programmable and by default, it will protect the selected zones.
blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these
blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to
different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause
problems in certain peripheral applications where the user expected the write to occur first (as written).
The C28x CPU supports a block protection mode where a region of memory can be protected so as to
make sure that operations occur as written (the penalty is extra cycles are added to align the operations).
This mode is programmable and by default, it will protect the selected zones.
The wait-states for the various spaces in the memory map area are listed in
Table 3-1. Wait-states
WAIT-STATES
WAIT-STATES
AREA
COMMENTS
(CPU)
(DMA)
(1)
M0 and M1 SARAMs
0-wait
No access
Fixed
Peripheral Frame 0
0-wait (writes)
No access (writes)
1-wait (reads)
0-wait (reads)
Peripheral Frame 3
0-wait (writes)
0-wait (writes)
Assumes no conflicts between CPU and DMA.
2-wait (reads)
1-wait (reads)
Peripheral Frame 1
0-wait (writes)
Cycles can be extended by peripheral generated ready.
No access
2-wait (reads)
Consecutive writes to the CAN will experience a 1-cycle
pipeline hit.
pipeline hit.
Peripheral Frame 2
0-wait (writes)
Fixed. Cycles cannot be extended by the peripheral.
No access
2-wait (reads)
L0 SARAM
0-wait data and
Assumes no CPU conflicts
program
L1 SARAM
L2 SARAM
L3 SARAM
L4 SARAM
1-wait
Assumes no conflicts between CPU and DMA
L5 SARAM
L6 SARAM
1-wait
L7 SARAM
XINTF
Programmable
Programmed via the XTIMING registers or extendable via
external XREADY signal.
external XREADY signal.
1-wait minimum
1-wait is minimum wait states allowed on external waveforms
for both reads and writes on XINTF.
for both reads and writes on XINTF.
0-wait minimum writes
0-wait data (write)
0-wait minimum for writes assumes write buffer enabled and
with write buffer
0-wait data (read)
not full.
enabled
Assumes no conflicts between CPU and DMA. When DMA
and CPU attempt simultaneous conflict, 1-cycle delay is
added for arbitration.
and CPU attempt simultaneous conflict, 1-cycle delay is
added for arbitration.
H0 SARAM
1-wait
A program-access prefetch mechanism is enabled on these
memories to improve instruction fetch performance for linear
memories to improve instruction fetch performance for linear
H1 SARAM
code execution.
H2 SARAM
No access
H3 SARAM
H4 SARAM
H5 SARAM
Boot-ROM
1-wait
No access
(1)
The DMA has a base of 4 cycles/word.
Copyright © 2009–2012, Texas Instruments Incorporated
Functional Overview
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