Texas Instruments IC FLPT TMS320C28346ZFET PBGA-256 TID TMS320C28346ZFET 데이터 시트
제품 코드
TMS320C28346ZFET
SPRS516D – MARCH 2009 – REVISED AUGUST 2012
3.2
Brief Descriptions
3.2.1
C28x CPU
The C2834x (C28x+FPU) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The
C28x+FPU based controllers have the same 32-bit fixed-point architecture as TI's existing C28x MCUs,
but also include a single-precision (32-bit) IEEE 754 floating-point unit (FPU). It is a very efficient C/C++
engine, enabling users to develop their system control software in a high-level language. It also enables
math algorithms to be developed using C/C++. The device is as efficient at DSP math tasks as it is at
system control tasks. This efficiency removes the need for a second processor in many systems. The 32 x
32-bit MAC 64-bit processing capabilities enable the controller to handle higher numerical resolution
problems efficiently. Add to this the fast interrupt response with automatic context save of critical registers,
resulting in a device that is capable of servicing many asynchronous events with minimal latency. The
device has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables it
to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-
ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations
further improve performance.
C28x+FPU based controllers have the same 32-bit fixed-point architecture as TI's existing C28x MCUs,
but also include a single-precision (32-bit) IEEE 754 floating-point unit (FPU). It is a very efficient C/C++
engine, enabling users to develop their system control software in a high-level language. It also enables
math algorithms to be developed using C/C++. The device is as efficient at DSP math tasks as it is at
system control tasks. This efficiency removes the need for a second processor in many systems. The 32 x
32-bit MAC 64-bit processing capabilities enable the controller to handle higher numerical resolution
problems efficiently. Add to this the fast interrupt response with automatic context save of critical registers,
resulting in a device that is capable of servicing many asynchronous events with minimal latency. The
device has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables it
to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-
ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations
further improve performance.
3.2.2
Memory Bus (Harvard Bus Architecture)
As with many MCU type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read
and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory
bus accesses can be summarized as follows:
peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read
and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory
bus accesses can be summarized as follows:
Highest:
Data Writes
(Simultaneous data and program writes cannot occur on the
memory bus.)
memory bus.)
Program Writes (Simultaneous data and program writes cannot occur on the
memory bus.)
Data Reads
Program
(Simultaneous program reads and fetches cannot occur on the
Reads
memory bus.)
Lowest:
Fetches
(Simultaneous program reads and fetches cannot occur on the
memory bus.)
memory bus.)
3.2.3
Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the
C2834x devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge
multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of
16 address lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral
bus are supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version
supports both 16- and 32-bit accesses (called peripheral frame 1). The third version supports DMA access
and both 16- and 32-bit accesses (called peripheral frame 3).
C2834x devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge
multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of
16 address lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral
bus are supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version
supports both 16- and 32-bit accesses (called peripheral frame 1). The third version supports DMA access
and both 16- and 32-bit accesses (called peripheral frame 3).
40
Functional Overview
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