Texas Instruments THS5651A Evaluation Module THS5651EVM THS5651EVM 데이터 시트
제품 코드
THS5651EVM
J1
J3
Control
Interface
Buffers
D[0–15]
DAC
14
DP
Amplifier
Interface
Interface
Transformer
Interface
J8
J9
J7
J6
J4
5 VA
AGND
–5 VA
AGND
–5 VA
J2
3.3 V (DV
DD
)
DGND
C54x/C54xx Interface
Pattern Generator Interface
System Block Diagram
1.1
System Block Diagram
The THS56X1 EVM provides a practical platform for evaluating the following devices:
•
THS5671A 14-bit resolution, 100 MSPS CommsDAC
•
THS5661A 12-bit resolution, 100 MSPS CommsDAC
•
TLV5651A 10-bit resolution, 100 MSPS CommsDAC
•
THS5641A 8-bit resolution, 100 MSPS CommsDAC
The EVM supports the SOIC (DW) package style, but all devices are available in other packages (see
Table 1-1. Package Styles Available
DA Package
(1)
DW Package
(2)
PW Package
(3)
Device
Supported?
Supported?
Supported?
THS5671A
No
Yes, 28 pins
Yes, 28 pins
THS5661A
No
Yes, 28 pins
Yes, 28 pins
THS5651A
No
Yes, 28 pins
Yes, 28 pins
THS5641A
No
Yes, 28 pins
Yes, 28 pins
(1)
The DA package is a TSSOP device, with pins on a 0.65
–
mm pitch.
(2)
The DW package is a small outline (SOIC) device, with pins on a 1.27
–
mm pitch.
(3)
The PW package is a TSSOP device, with pins on a 0.65
–
mm pitch.
A block diagram for the THS56X1 EVM is drawn in
. The important features of each component
of the block diagram are discussed at length in Section 1.2.
Figure 1-1. THS56X1 EVM Block Diagram
8
EVM Overview
SLAU032C
–
February 2001
–
Revised April 2011
Copyright
©
2001
–
2011, Texas Instruments Incorporated