Texas Instruments Evaluation Board for the LM25066I LM25066I-EVM/NOPB LM25066I-EVM/NOPB 데이터 시트
제품 코드
LM25066I-EVM/NOPB
SNVS824C – JUNE 2012 – REVISED MARCH 2013
voltage at the FB pin is below its threshold, the 24 µA current source at FB is disabled. As the output voltage
increases, taking FB above its threshold, the current source is enabled, sourcing current out of the pin, raising
the voltage at FB to provide threshold hysteresis. The PGD output is forced low when either the UVLO/EN pin is
below its threshold or the OVLO pin is above its threshold. The status of the PGD pin can be read via the PMBus
interface in either the STATUS_WORD (79h) or DIAGNOSTIC_WORD (E1h) registers.
increases, taking FB above its threshold, the current source is enabled, sourcing current out of the pin, raising
the voltage at FB to provide threshold hysteresis. The PGD output is forced low when either the UVLO/EN pin is
below its threshold or the OVLO pin is above its threshold. The status of the PGD pin can be read via the PMBus
interface in either the STATUS_WORD (79h) or DIAGNOSTIC_WORD (E1h) registers.
VDD Sub-Regulator
The LM25066I/A contains an internal linear sub-regulator which steps down the input voltage to generate a 4.5V
rail used for powering low voltage circuitry. When the input voltage is below 4.5V, VDD will track VIN. For input
voltages 3.3V and below, VDD should be tied directly to VIN to avoid the dropout of the sub-regulator. The VDD
sub-regulator should be used as the pullup supply for the CL, CB, RETRY, ADR2, ADR1, ADR0 pins if they are
to be tied high. It may also be used as the pullup supply for the PGD and the SMBus signals (SDA, SCL, SMBA).
The VDD sub-regulator is not designed to drive high currents and should not be loaded with other integrated
circuits. The VDD pin is current limited to 45mA in order to protect the LM25066I/A in the event of a short. The
sub-regulator requires a bypass capacitance having a value between 1 µF and 4.7 µF to be placed as close to
the VDD pin as the PCB layout allows.
rail used for powering low voltage circuitry. When the input voltage is below 4.5V, VDD will track VIN. For input
voltages 3.3V and below, VDD should be tied directly to VIN to avoid the dropout of the sub-regulator. The VDD
sub-regulator should be used as the pullup supply for the CL, CB, RETRY, ADR2, ADR1, ADR0 pins if they are
to be tied high. It may also be used as the pullup supply for the PGD and the SMBus signals (SDA, SCL, SMBA).
The VDD sub-regulator is not designed to drive high currents and should not be loaded with other integrated
circuits. The VDD pin is current limited to 45mA in order to protect the LM25066I/A in the event of a short. The
sub-regulator requires a bypass capacitance having a value between 1 µF and 4.7 µF to be placed as close to
the VDD pin as the PCB layout allows.
Remote Temperature Sensing
The LM25066I/A is designed to measure temperature remotely using an MMBT3904 NPN transistor. The base
and collector of the MMBT3904 is connected to the DIODE pin and the emitter is grounded. Place the
MMBT3904 near the device whose temperature is to be monitored. If the temperature of the hot-swap pass
MOSFET, Q
and collector of the MMBT3904 is connected to the DIODE pin and the emitter is grounded. Place the
MMBT3904 near the device whose temperature is to be monitored. If the temperature of the hot-swap pass
MOSFET, Q
1
, is to be measured, the MMBT3904 should be placed as close to Q
1
as the layout allows. The
temperature is measured by means of a change in the diode voltage in response to a step in current supplied by
the DIODE pin. The DIODE pin sources a constant 9.4 µA but pulses 250 µA once every millisecond in order to
measure the diode temperature. Care must be taken in the PCB layout to keep the parasitic resistance between
the DIODE pin and the MMBT3904 low so as not to degrade the measurement. Additionally, a small 1000 pF
bypass capacitor should be placed in parallel with the MMBT3904 to reduce the effects of noise. The
temperature can be read using the READ_TEMPERATURE_1 PMBus command (8Dh). The default limits of the
LM25066I/A will cause SMBA pin to be pulled low if the measured temperature exceeds 125°C and will disable
the hot-swap pass MOSFET if the temperature exceeds 150°C. These thresholds can be reprogrammed via the
PMBus interface using the OT_WARN_LIMIT (51h) and OT_FAULT_LIMIT (4Fh) commands. If the temperature
measurement and protection capability of the LM25066I/A is not used, the DIODE pin should be grounded.
the DIODE pin. The DIODE pin sources a constant 9.4 µA but pulses 250 µA once every millisecond in order to
measure the diode temperature. Care must be taken in the PCB layout to keep the parasitic resistance between
the DIODE pin and the MMBT3904 low so as not to degrade the measurement. Additionally, a small 1000 pF
bypass capacitor should be placed in parallel with the MMBT3904 to reduce the effects of noise. The
temperature can be read using the READ_TEMPERATURE_1 PMBus command (8Dh). The default limits of the
LM25066I/A will cause SMBA pin to be pulled low if the measured temperature exceeds 125°C and will disable
the hot-swap pass MOSFET if the temperature exceeds 150°C. These thresholds can be reprogrammed via the
PMBus interface using the OT_WARN_LIMIT (51h) and OT_FAULT_LIMIT (4Fh) commands. If the temperature
measurement and protection capability of the LM25066I/A is not used, the DIODE pin should be grounded.
Damaged MOSFET Detection
The LM25066I/A is able to detect whether the external MOSFET, Q
1
, is damaged under certain conditions. If the
voltage across the sense resistor exceeds 4mV while the GATE voltage is low or the internal logic indicates that
the GATE should be low, the EXT_MOSFET_SHORTED bit in the STATUS_MFR_SPECIFIC (80h) and
DIAGNOSTIC_WORD (E1h) registers will be toggled high and the SMBA pin will be pulled low unless this
feature is disabled using the ALERT_MASK register (D8h). This method effectively determines whether Q
the GATE should be low, the EXT_MOSFET_SHORTED bit in the STATUS_MFR_SPECIFIC (80h) and
DIAGNOSTIC_WORD (E1h) registers will be toggled high and the SMBA pin will be pulled low unless this
feature is disabled using the ALERT_MASK register (D8h). This method effectively determines whether Q
1
is
shorted because of damage present between the drain and gate and/or drain and source of the external
MOSFET.
MOSFET.
Enabling, Disabling, and Resetting
The output can be disabled at any time during normal operation by either pulling the UVLO/EN pin to below its
threshold or the OVLO pin above its threshold, causing the GATE voltage to be forced low with a pulldown
strength of 2mA. Toggling the UVLO/EN pin will also reset the LM25066I/A from a latched-off state due to an
over-current or over-power limit condition which has caused the maximum allowed number of retries to be
exceeded. While the UVLO/EN or OVLO pins can be used to disable the output, they have no effect on the
volatile memory or address location of the LM25066I/A. User stored values for address, device operation, and
warning and fault levels programmed via the SMBus are preserved while the LM25066I/A is powered regardless
of the state of the UVLO/EN and OVLO pins. The output may also be enabled or disabled by writing 80h or 0h to
the OPERATION (03h) register. To re-enable after a fault, the fault condition should be cleared and the
OPERATION (03h) register should be written to 0h and then 80h.
threshold or the OVLO pin above its threshold, causing the GATE voltage to be forced low with a pulldown
strength of 2mA. Toggling the UVLO/EN pin will also reset the LM25066I/A from a latched-off state due to an
over-current or over-power limit condition which has caused the maximum allowed number of retries to be
exceeded. While the UVLO/EN or OVLO pins can be used to disable the output, they have no effect on the
volatile memory or address location of the LM25066I/A. User stored values for address, device operation, and
warning and fault levels programmed via the SMBus are preserved while the LM25066I/A is powered regardless
of the state of the UVLO/EN and OVLO pins. The output may also be enabled or disabled by writing 80h or 0h to
the OPERATION (03h) register. To re-enable after a fault, the fault condition should be cleared and the
OPERATION (03h) register should be written to 0h and then 80h.
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