Texas Instruments Evaluation Board for the LM25066I LM25066I-EVM/NOPB LM25066I-EVM/NOPB 데이터 시트
제품 코드
LM25066I-EVM/NOPB
OUT
UVLO/EN
VIN
GATE
DIODE
ADR2
ADR1
ADR0
VDD
N/C
25 k
:
2.1 k
:
2.1 k
:
FB
10 k
:
1.3 k
:
MMBT3904
OVLO
SDA
SCL
PGD
N/C
SENSE
VDD
SMBus
Interface
SMBA
CL
CB
RETRY
VAUX
VDD
VREF
TIMER
PWR
GND
LM25066I/IA
Auxillary ADC Input
(0V - 1.16V)
(0V - 1.16V)
V
OUT
330
P
F
10 k
:
0.5 m
:
12V
1
P
F
1
P
F
6.98 k
:
0.47
P
F
SMC
J
1
5
A
PSMN1R2-25YL
UVLO/EN
OUT
SNVS824C – JUNE 2012 – REVISED MARCH 2013
APPLICATIONS SECTION
Figure 36. Typical Application Circuit
DESIGN-IN PROCEDURE
(Refer to
for Typical Application Circuit) Shown here is the step-by-step procedure for hardware design
of the LM25066I/A. This procedure refers to sections that provide detailed information on the following design
steps. The recommended design-in procedure is as follows:
steps. The recommended design-in procedure is as follows:
MOSFET Selection: Determine MOSFET value based on breakdown voltage, current and power ratings.
Current Limit, R
S
: Determine the current limit threshold (I
LIM
). This threshold must be higher than the normal
maximum load current, allowing for tolerances in the current sense resistor value and the LM25066I/A Current
Limit threshold voltage. Use
Limit threshold voltage. Use
to determine the value for R
S
.
Power Limit Threshold: Determine the maximum allowable power dissipation for the series pass MOSFET (Q
1
)
using the device’s SOA information. Use
to determine the value for R
PWR
.
Turn-On Time and TIMER Capacitor, C
T
: Determine the value for the timing capacitor at the TIMER pin (C
T
)
using
. The fault timeout period (t
FAULT
) MUST be longer than the circuit’s turn-on-time. The turn-on
time can be estimated using the equations in
, but should be verified experimentally. Review the
resulting insertion time, and the restart timing if retry is enabled.
UVLO, OVLO: Choose option A, B, C, or D from
to set the UVLO and OVLO thresholds and
hysteresis. Use the procedure for the appropriate option to determine the resistor values at the UVLO/EN and
OVLO pins.
OVLO pins.
Power Good: Choose the appropriate output voltage and calculate the required resistor divider from the output
voltage to the FB pin. Choose either VDD or OUT to connect properly sized pullup resistor for the Power Good
output (PGD).
voltage to the FB pin. Choose either VDD or OUT to connect properly sized pullup resistor for the Power Good
output (PGD).
Refer to Programming Guide section: After all hardware design is complete, refer to the programming guide
for a step by step procedure regarding software.
for a step by step procedure regarding software.
MOSFET SELECTION
It is recommended that the external MOSFET (Q
1
) selection be based on the following criteria:
Copyright © 2012–2013, Texas Instruments Incorporated
21
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