Texas Instruments Evaluation Board for the LM25066I LM25066I-EVM/NOPB LM25066I-EVM/NOPB 데이터 시트
제품 코드
LM25066I-EVM/NOPB
SNVS824C – JUNE 2012 – REVISED MARCH 2013
WARNING
Inhibiting the MOSFET switch off in response to over-current or circuit breaker
fault conditions will likely result in the destruction of the MOSFET! This
functionality should be used with great care and supervision!
fault conditions will likely result in the destruction of the MOSFET! This
functionality should be used with great care and supervision!
Table 31. GATE_MASK Register
Bit
NAME
Default
7
Not used, always 0
0
6
Not used, always 0
0
5
VIN UV FAULT
0
4
VIN OV FAULT
0
3
IIN/PFET FAULT
0
2
OVERTEMP FAULT
0
1
Not used, always 0
0
0
CIRCUIT BREAKER FAULT
0
The IIN/PFET Fault refers to the input current fault and the MOSFET power dissipation fault. There is no input
power fault detection, only input power warning detection.
power fault detection, only input power warning detection.
MFR_SPECIFIC_08: ALERT_MASK (D8h)
The ALERT_MASK is used to mask the SMBA when a specific fault or warning has occurred. Each bit
corresponds to one of the 14 different analog and digital faults or warnings that would normally result in an
SMBA being set. When the corresponding bit is high, that condition will not cause the SMBA to be asserted. If
that condition occurs, the registers where that condition is captured will still be updated (STATUS registers,
DIAGNOSTIC_WORD) and the external MOSFET gate control will still be active (VIN_OV_FAULT,
VIN_UV_FAULT, IIN/PFET_FAULT, CB_FAULT, OT_FAULT). This register is accessed with the PMBus™ Read
/ Write Word protocol. The VIN UNDERVOLTGE FAULT flag will default to 1 on startup. However, it will be
cleared to 0 after the first time the input voltage exceeds the resistor programmed UVLO threshold.
corresponds to one of the 14 different analog and digital faults or warnings that would normally result in an
SMBA being set. When the corresponding bit is high, that condition will not cause the SMBA to be asserted. If
that condition occurs, the registers where that condition is captured will still be updated (STATUS registers,
DIAGNOSTIC_WORD) and the external MOSFET gate control will still be active (VIN_OV_FAULT,
VIN_UV_FAULT, IIN/PFET_FAULT, CB_FAULT, OT_FAULT). This register is accessed with the PMBus™ Read
/ Write Word protocol. The VIN UNDERVOLTGE FAULT flag will default to 1 on startup. However, it will be
cleared to 0 after the first time the input voltage exceeds the resistor programmed UVLO threshold.
Table 32. ALERT_MASK Definitions
BIT
NAME
DEFAULT
15
VOUT UNDERVOLTAGE WARN
1
14
IIN LIMIT Warn
1
13
VIN UNDERVOLTAGE WARN
1
12
VIN OVERVOLTAGE WARN
1
11
POWER GOOD
1
10
OVERTEMP WARN
1
9
Not Used, always 0
0
8
OVERPOWER LIMIT WARN
1
7
Not Used, always 0
0
6
EXT_MOSFET_SHORTED
0
5
VIN UNDERVOLTAGE FAULT
(1)
0
4
VIN OVERVOLTAGE FAULT
0
3
IIN/PFET FAULT
0
2
OVERTEMPERATURE FAULT
1
1
CML FAULT (Communications Fault)
0
0
CIRCUIT BREAKER FAULT
0
(1)
VIN_UV_FAULT initializes after power up as masked. When VIN exceeds the hardware threshold the mask bit is automatically cleared.
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