Texas Instruments DS100BR410 Low Pwr Quad Ch Repeater with 10.3125 Gbps Eq and De-Emphasis Driver EVM DS100BR410EVK-4/NO DS100BR410EVK-4/NOPB 데이터 시트
제품 코드
DS100BR410EVK-4/NOPB
SNLS326B – OCTOBER 2010 – REVISED APRIL 2013
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SDC is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SDC is High indicates a message STOP condition.
IDLE: If SDC and SDA are both High for a time exceeding t
BUF
from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for t
HIGH
then the bus will transfer to the IDLE state.
SMBus Transactions
The device supports WRITE, Burst WRITE, READ. and Burst READ transactions. See
for register
address, type (Read/Write, Read Only), default value and function information.
Writing a Register
To write a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host (Master) selects the device by driving its SMBus Chip Select (CS) signal High.
2. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
3. The Device (Slave) drives the ACK bit (“0”).
4. The Host drives the 8-bit Register Address.
5. The Device drives an ACK bit (“0”).
6. The Host drive the 8-bit data byte.
7. The Device drives an ACK bit (“0”).
8. The Host drives a STOP condition.
9. The Host de-selects the device by driving its SMBus CS signal Low.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.
now occur.
Reading a Register
To read a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host (Master) selects the device by driving its SMBus Chip Select (CS) signal High.
2. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
3. The Device (Slave) drives the ACK bit (“0”).
4. The Host drives the 8-bit Register Address.
5. The Device drives an ACK bit (“0”).
6. The Host drives a START condition.
7. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
8. The Device drives an ACK bit “0”.
9. The Device drives the 8-bit data value (register contents).
10. The Host drives a NACK bit “1”indicating end of the READ transfer.
11. The Host drives a STOP condition.
12. The Host de-selects the device by driving its SMBus CS signal Low.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now
occur.
occur.
Information on the Registers
The status registers 01'h to 03'h provide information of the channel that is selected. The information provided are
the OOB_DIS, EN, EQ Boost, VOD and DEM bits of the selected channel. By default, channel 0 is selected. In
order to change the selected channel, write to reg_07 bit[5:4]. Write a 1 to reg_07 bit[0] is also needed to allow
the registers 13'h to 1A'h to control the channel EN and EQ boost bits of each of the channels. Each channel can
be individually enabled (EN) and set to a desired boost level with these registers. Please refer to
the OOB_DIS, EN, EQ Boost, VOD and DEM bits of the selected channel. By default, channel 0 is selected. In
order to change the selected channel, write to reg_07 bit[5:4]. Write a 1 to reg_07 bit[0] is also needed to allow
the registers 13'h to 1A'h to control the channel EN and EQ boost bits of each of the channels. Each channel can
be individually enabled (EN) and set to a desired boost level with these registers. Please refer to
for
additional information.
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