Texas Instruments DS100BR410 Low Pwr Quad Ch Repeater with 10.3125 Gbps Eq and De-Emphasis Driver EVM DS100BR410EVK-4/NO DS100BR410EVK-4/NOPB 데이터 시트
제품 코드
DS100BR410EVK-4/NOPB
IN_n+
IN_n-
EQ
LIMITER
IDLE
DET
OUTBUF
BST[2]
OUT_n+
OUT_n-
BST[1]
BST[0]
BST[0]
SMBus
SMBu
s
SMBus
EN
n
SD
n
CS
PI
N_
Mo
d
e
SDA
SDC
SMBus
1 of 4 Channels - DS100BR410
O
O
B_D
IS
VO
D
_
SEL
D
E
_
SEL
SNLS326B – OCTOBER 2010 – REVISED APRIL 2013
FUNCTIONAL DESCRIPTION
DS100BR410 Functional Descriptions
The DS100BR410 is a Low Power Quad Channel Repeater with Equalizer and De-Emphasis Driver optimized for
operation up to 10.3125 Gbps for backplane and cable applications.
operation up to 10.3125 Gbps for backplane and cable applications.
DATA CHANNELS
The DS100BR410 provides four data channels. Each data channel consists of an equalizer stage, a limiting
amplifier, a DC offset correction block, and a CML driver as shown in
amplifier, a DC offset correction block, and a CML driver as shown in
Figure 7. Simplified Block Diagram
EQUALIZER BOOST CONTROL
Each data channel support eight programmable levels of equalization boost. The state of the PIN_MODE control
input determines how the boost settings are controlled. If PIN_MODE is held High, then the equalizer boost
setting is controlled by the Boost Set pins (BST_[2:0]) in accordance with
input determines how the boost settings are controlled. If PIN_MODE is held High, then the equalizer boost
setting is controlled by the Boost Set pins (BST_[2:0]) in accordance with
. If this programming method is
chosen, then the boost setting selected on the Boost Set pins is applied to all channels. When PIN_MODE is
held Low, the equalizer boost level is controlled through the SMBus. This programming method is accessed via
the appropriate SMBus registers (see
held Low, the equalizer boost level is controlled through the SMBus. This programming method is accessed via
the appropriate SMBus registers (see
). Using this approach, equalizer boost settings can be
programmed for each channel individually. PIN_MODE is internally pulled High, therefore if left open, the boost
settings are controlled by the Boost Set pins (BST_[2:0]). The eight levels of boost settings enables the
DS100BR410 to address a wide range of media loss and data rates.
settings are controlled by the Boost Set pins (BST_[2:0]). The eight levels of boost settings enables the
DS100BR410 to address a wide range of media loss and data rates.
Table 1. Boost / EQ Pin Mode Configuration
SMBus
Inputs
Register Bits
Result @ 5 GHz
BST_2
BST_1
BST_0
[8:0]
0
0
0
000000000
2.7 dB
0
0
1
000000001
7.3 dB
0
1
0
000000011
12.2 dB
0
1
1
000000111
16.6 dB
1
0
0
000001111
20.6 dB
1
0
1
000011111
24.8 dB
1
1
0
000101111
27.6 dB (default)
1
1
1
000111111
28.9 dB
Copyright © 2010–2013, Texas Instruments Incorporated
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