Texas Instruments DS100BR410 Low Pwr Quad Ch Repeater with 10.3125 Gbps Eq and De-Emphasis Driver EVM DS100BR410EVK-4/NO DS100BR410EVK-4/NOPB 데이터 시트
제품 코드
DS100BR410EVK-4/NOPB
SNLS326B – OCTOBER 2010 – REVISED APRIL 2013
Table 4. DS100BR410 Register Map (continued)
ADD
Default
REG Name
Bit(s)
Field
Type
Description
(hex)
(binary)
19
Channel 0
7:5
Reserved
R/W
000
EN and EQ
4
Channel Enable
R/W
1
0 = Disabled
Control
1 = Enabled
3:1
Reserved
R/W
000
0
Boost[8]
R/W
0
See
1A
EQ Control
7:0
Boost[7:0]
R/W
00000000
See
Channel 0
Table 5. Boost / EQ SMBus Register: 16 levels - recommended settings
Boost Register Bits
Result
bit[8]
bit[7]
bit[6]
bit[5]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
@ 5.5 GHz
0
0
0
0
0
0
0
0
0
000'h - 2.7 dB (BST_[2:0]=000)
0
0
0
0
0
0
0
0
1
001'h - 7.3 dB (BST_[2:0]=001)
0
0
0
0
0
0
0
1
0
002'h - 10.3 dB
0
0
0
0
0
0
0
1
1
003'h - 12.2 dB (BST_[2:0]=010)
0
0
0
0
0
0
1
1
1
007'h - 16.6 dB (BST_[2:0]=011)
0
0
0
0
1
0
1
0
1
015'h - 17 dB
0
0
0
0
0
1
0
1
1
00B'h - 19.2 dB
0
0
0
0
0
1
1
1
1
00F'h - 20.6 dB (BST_[2:0]=100)
0
0
1
0
1
0
1
0
1
055'h - 21.9 dB
0
0
0
0
1
1
1
1
1
01F'h - 24.8 dB (BST_[2:0]=101)
0
0
0
1
0
1
1
1
1
02F'h - 27.6 dB (BST_[2:0]=110)
0
0
0
1
1
1
1
1
1
03F'h - 28.9 dB (BST_[2:0]=111)
0
1
0
1
0
1
0
1
0
0AA'h - 31.3 dB
0
0
1
1
1
1
1
1
1
07F'h - 33.3 dB
0
1
0
1
1
1
1
1
1
0BF'h - 35.7 dB
0
1
1
1
1
1
1
1
1
0FF'h - 37 dB
Applications Information
GENERAL RECOMMENDATIONS
The DS100BR410 is a high performance circuit capable of delivering excellent performance up to 10.3125 Gbps.
Careful attention must be paid to the details associated with high-speed design as well as providing a clean
power supply. Refer to the LVDS Owner's Manual for more detailed information on high speed design tips to
address signal integrity design issues.
Careful attention must be paid to the details associated with high-speed design as well as providing a clean
power supply. Refer to the LVDS Owner's Manual for more detailed information on high speed design tips to
address signal integrity design issues.
UNUSED CHANNEL
It is recommended to disable the unused channel (EN[3:0] = LOW). The power consumption of the device is
reduced when the channel is disabled.
reduced when the channel is disabled.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The high speed CML inputs and outputs must have a controlled differential impedance of 100
Ω
. It is preferable to
route differential lines exclusively on one layer of the board, particularly for the input traces. The use of vias
should be avoided if possible. If vias must be used, they should be used sparingly and must be placed
symmetrically for each side of a given differential pair. Route the differential signals away from other signals and
noise sources on the printed circuit board. See AN-1187 (
should be avoided if possible. If vias must be used, they should be used sparingly and must be placed
symmetrically for each side of a given differential pair. Route the differential signals away from other signals and
noise sources on the printed circuit board. See AN-1187 (
) for additional information on WQFN
packages.
14
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