Texas Instruments DS100BR410 Low Pwr Quad Ch Repeater with 10.3125 Gbps Eq and De-Emphasis Driver EVM DS100BR410EVK-4/NO DS100BR410EVK-4/NOPB 데이터 시트
제품 코드
DS100BR410EVK-4/NOPB
SNLS326B – OCTOBER 2010 – REVISED APRIL 2013
Impedance discontinuities at the differential via can be minimized or eliminated by increasing the swell around
each via hole. To further improve the signal quality, a ground via placed close to the signal via for a low
inductance return current path is recommended. When the via structure is associated with stripline trace and a
thick board, further optimization such as back drilling is often used to reduce the high frequency effects of via
stubs on the signal path. To minimize cross-talk coupling, it is recommended to have >3X gap spacing between
the differential pairs. For example, if the trace width is 5 mils with 5 mils spacing – 100
each via hole. To further improve the signal quality, a ground via placed close to the signal via for a low
inductance return current path is recommended. When the via structure is associated with stripline trace and a
thick board, further optimization such as back drilling is often used to reduce the high frequency effects of via
stubs on the signal path. To minimize cross-talk coupling, it is recommended to have >3X gap spacing between
the differential pairs. For example, if the trace width is 5 mils with 5 mils spacing – 100
Ω
differential impedance
(closely coupled). The gap spacing between the differential pairs should be >15 mils.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the DS100BR410 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers
of the printed circuit board. The layer thickness of the dielectric should be minimized so that the V
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers
of the printed circuit board. The layer thickness of the dielectric should be minimized so that the V
DD
and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.1uF or 0.01
bypassing through the proper use of bypass capacitors is required. A 0.1uF or 0.01
μ
F bypass capacitor should
be connected to each V
DD
pin such that the capacitor is placed as close as possible to the DS100BR410.
Smaller body size capacitors can help facilitate proper component placement. Additionally, three capacitors with
capacitance in the range of 2.2
capacitance in the range of 2.2
μ
F to 10
μ
F should be incorporated in the power supply bypassing design as
well. These capacitors can be either tantalum or an ultra-low ESR ceramic.
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