Texas Instruments XILINXPWR-081 Evaluation Module for Xilinx FPGAs XILINXPWR-081 XILINXPWR-081 데이터 시트
제품 코드
XILINXPWR-081
SLVL004
-
-
Link to datasheets at http://focus.ti.com/lit/ds/symlink/TPS78601.pdf,
http://focus.ti.com/lit/ds/symlink/tps79601.pdf,
http://focus.ti.com/lit/ds/symlink/tps79401.pdf, and
http://focus.ti.com/lit/ds/symlink/tps3809k33.pdf.
http://focus.ti.com/lit/ds/symlink/tps79601.pdf,
http://focus.ti.com/lit/ds/symlink/tps79401.pdf, and
http://focus.ti.com/lit/ds/symlink/tps3809k33.pdf.
-
-
Link to application note SLVA118 http://focus.ti.com/lit/an/slva118/slva118.pdf
to explore the thermal considerations when using linear regulators.
to explore the thermal considerations when using linear regulators.
-
-
Link to application note SLVA156 http://focus.ti.com/lit/an/slva156/slva156.pdf
for more details on the soft-start circuit.
for more details on the soft-start circuit.
-
-
Link to application note SLVA159
http://focus.ti.com/lit/an/slva159a/slva159a.pdf when using 3.3-V JTAG ports.
http://focus.ti.com/lit/an/slva159a/slva159a.pdf when using 3.3-V JTAG ports.
IMPLEMENTATION NOTES:
-
-
Sequencing: Although Xilinx FPGAs do NOT require it, this reference design
employs sequencing. This practice is consistent with good power supply design
and prevents the input power supply from being pulled down due to supporting
in-rush currents for charging large capacitive loads all at once.
employs sequencing. This practice is consistent with good power supply design
and prevents the input power supply from being pulled down due to supporting
in-rush currents for charging large capacitive loads all at once.
-
-
V
CCO
minimum ramp time: Met by soft-start circuit consisting of the external
PMOS transistor Q3 and supporting passive components.
-
-
Power Dissipation/Thermal Issues: The DDPAK packaged regulators in this
design are limited to 3W @ T
design are limited to 3W @ T
A
= 55
o
C and no airflow, due to power dissipation
limitation of the package.
o
Refer to the application section of the datasheet for maximum power
dissipation at different ambient conditions as well as guidance on sizing
the ground plane area underneath the package for heatsinking.
the ground plane area underneath the package for heatsinking.
o
The linear regulator’s output current can be computed by rearranging the
following equation:
P
Dmax
= (V
IN
– V
CCINT
) * I
CCINTmax
.
As an example, with V
CCINT
= 1.2V and P
Dmax
= 3 W:
§
§
I
CCINTmax
= P
Dmax
/(V
IN
– V
CCINT
).
§
§
I
CCINTmax =
1.4 A when V
IN
= 3.3 V so use the TPS78601 for U2.
§
§
I
CCINTmax =
789 mA when V
IN
= 5.0 V so use the TPS79601 for U2.
-
-
Soft Start Circuitry:
o
NMOS transistor Q4 should be selected so that its threshold voltage, V
T H
,
is at least 0.9 V below V
IN
or lower (e.g., V
T H
< 5.0 V – 1.2 V = 3.8 V or
V
T H
< 3.3 V – 1.2 V = 2.1 V). In addition, the transistor’s R
DSon
should be
low enough, when driven by V
IN
, that the voltage drop across the
transistor at maximum current (e.g., I
CCINTmax
*R
DSon
) does not cause
V
CCINT
to fall below its -5% tolerance.
o
PMOS transistor Q3 should be selected so that its threshold voltage, V
T H
,
is at least 0.9 V below the V
CCO
voltage or lower (e.g., V
T H
< 3.3 V – 0.9
V = 2.4 V). In addition, the transistor’s R
DSon
should be low enough,
when driven by V
CCO
= 3.3 V, that the voltage drop across the transistor at