Texas Instruments XILINXPWR-081 Evaluation Module for Xilinx FPGAs XILINXPWR-081 XILINXPWR-081 데이터 시트
제품 코드
XILINXPWR-081
SLVL004
maximum current (e.g., I
CCO
*R
DSon
) does not cause V
CCO
to fall below its -
5% tolerance.
o
The source of Q4 and the drain of Q3 each need at least 10 uF of
capacitance in order for the soft-start circuits to work properly. The
additional bulk bypass capacitance (not shown in the schematic) required
for each rail of the FPGA will most likely meet this requirement.
additional bulk bypass capacitance (not shown in the schematic) required
for each rail of the FPGA will most likely meet this requirement.
-
-
Modifications:
o
Adapt for 3.3 V input supply by:
§
§
Omitting U3 V
CCO
linear regulator,
§
§
Replacing U2, TPS79601 1-A linear regulator, with TPS78601
1.5-A linear regulator,
1.5-A linear regulator,
§
§
Replacing U1 SVS, TPS3809K33, with TPS3809L30,
§
§
Resizing R4 to XXX.
o
For a low-cost, discrete Supply Voltage Supervisory Circuit alternative to
U1, please see reference design PR286 (Active-High Reset Output) or
PR281 (Active-Low Reset Output).
PR281 (Active-Low Reset Output).
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-
3.3V Co nfiguration
o
The Spartan-3 FPGA configuration and JTAG ports commonly use signals
with a 2.5-V swing. Alternatively, it is possible to use 3.3-V signals
simply by adding a few external resistors. The 3.3-V signals can cause a
reverse current that flows from certain configurations and JTAG input pins,
through the FPGA, to the V
simply by adding a few external resistors. The 3.3-V signals can cause a
reverse current that flows from certain configurations and JTAG input pins,
through the FPGA, to the V
CCAUX
power rail. Therefore, please refer to
application note SLVA159 http://focus.ti.com/lit/an/slva159a/slva159a.pdf
for implementation guidance.
for implementation guidance.
QUESTIONS?
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-
Send an email to fpgasupport@list.ti.com