Texas Instruments Evaluation Module for Positive Voltage, Power-Limiting Hotswap Controller TPS24710EVM-003 TPS24710EVM-003 데이터 시트
제품 코드
TPS24710EVM-003
T
FLT
T
10 μA
C =
t
,
1.35 V
therefore,
10 μA
C =
7 ms
52 nF
1.35 V
´
´
=
ISS
FLT
ON
GATE
FLT
5.9 V C
t
t
,
I
therefore,
5.9 V 2040 pF
t
0.614 ms
1.22 ms
20 μA
´
=
+
´
=
+
=
ON
t
=
2
OUT
VCC(MAX)
OUT
VCC(MAX)
OUT
LIM
LIM
LIM
VCC(MAX)
2
LIM
LIM
LIM
C
V
C
V
C
P
if
P
I
V
2 P
I
2 I
´
´
´
+
-
<
´
´
´
OUT
VCC(MAX)
LIM
LIM
VCC(MAX)
LIM
C
V
if
P
I
V
I
´
>
´
(
)
(
)
2
ON
2
therefore,
470 μF
12 V
470 μF 29.3 W
470 μF 12 V
t
0.614 ms
2 29.3 W
12 A
2
12 A
´
´
´
=
+
-
=
´
´
SLVSAL2E – JANUARY 2011 – REVISED NOVEMBER 2013
STEP 4. Choose Output Voltage Rising Time, t
ON
, C
T
The maximum output voltage rise time, t
ON
, set by the timer capacitor C
T
must suffice to fully charge the load
capacitance C
OUT
without triggering the fault circuitry.
defines t
ON
for two possible inrush cases.
Assuming that only the load capacitance draws current during start-up,
(10)
The next step is to determine the minimum fault-timer period. In
, the output rise time is t
ON
. This is
the amount of time it takes to charge the output capacitor up to the final output voltage. However, the fault timer
uses the difference between the input voltage and the gate voltage to determine if the TPS24710/11/12/13 is still
in inrush limit. The fault timer continues to run until V
uses the difference between the input voltage and the gate voltage to determine if the TPS24710/11/12/13 is still
in inrush limit. The fault timer continues to run until V
GS
rises 5.9 V (for V
VCC
= 12 V) above the input voltage.
Some additional time must be added to the charge time to account for this additional gate voltage rise. The
minimum fault time can be calculated using
minimum fault time can be calculated using
(11)
where C
ISS
is the MOSFET input capacitance and I
GATE
is the minimum gate sourcing current of
TPS24710/11/12/13, or 20
μA. Using the example parameters in
and the CSD16403Q5 data sheet
) leads to a minimum fault time of 1.22 ms. This time is derived considering the tolerances of C
OUT
,
C
ISS
, I
LIM
, P
LIM
, I
GATE
, and V
VCC(MAX)
. The fault timer must be set to a value higher than 1.22 ms to avoid turning
off during start-up, but lower than any maximum fault time limit determined by the SOA curve (see
)
derated for operating junction temperature.
For this example, select 7 ms to allow for variation of system parameters such as temperature, load, component
tolerance, and input voltage. The timing capacitor is calculated in
tolerance, and input voltage. The timing capacitor is calculated in
as 52 nF. Selecting the next-highest
standard value, 56 nF, yields a 7.56-ms fault time (see
).
(12)
24
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