Texas Instruments DAC8871EVM - DAC8871EVM Evaluation Module DAC8871EVM DAC8871EVM 데이터 시트
제품 코드
DAC8871EVM
www.ti.com
3.3
Digital Control Interface
3.3.1
CS or FS Signal
3.3.2
SCLK Signal
3.3.3
SDI Signal
3.3.4
LDAC Signal
EVM Operation
The DAC8871 supports the standard high-speed SPI serial interface to communicate with
microprocessors or DSP devices. The EVM incorporates a pass-through connector to accommodate the
digital control interface to the DAC8871 device via J2 (top side) and P2 (bottom side) header/socket
connectors. The signals on this pass-through connector are shown in
microprocessors or DSP devices. The EVM incorporates a pass-through connector to accommodate the
digital control interface to the DAC8871 device via J2 (top side) and P2 (bottom side) header/socket
connectors. The signals on this pass-through connector are shown in
.
Table 3. Digital Control Interface Signal Mapping for J2/P2 Header/Socket Connectors
Pin Number
Signal
Function
J2.1/P2.1
CS
Primary synchronization and device enable input for the DAC8871. Host microcontroller’s STE
signal for SPI interface.
signal for SPI interface.
J2.3/P2.3
SCLK
Serial interface clock.
J2.5/P2.5
Unused
J2.7/P2.7
FS
Secondary synchronization and device enable input for the DAC8871. Host microcontroller’s
STE signal for SPI interface or FS signal from DSP host system.
STE signal for SPI interface or FS signal from DSP host system.
J2.9/P2/9
Unused
J2.11/P2.11
SDI
Serial data input.
J2.13/P2.13
Unused
J2.15/P2.15
GPIO1/INT
GPIO signal to control LDAC for DAC output latch update.
J2.17/P2.17
GPIO2/TOUT
Alternate GPIO signal to control LDAC for DAC output latch update.
J2.19/P2.19
RST
GPIO signal to control RST for DAC reset function.
The CS and FS signals of the EVM are interchangeable, and therefore the signal to be used depends on
the host controller that is selected to communicate with the DAC8871EVM. Either signal can be chosen to
drive the DAC8871 Chip Select (CS) pin. The basic function of the CS and FS signal is to drive the CS pin
of the DAC8871 to enable the device communication port and to synchronize the data going into the
device immediately following its high-to-low transition. This signal must be held low while the host
processor is accessing the DAC. The low-to-high transition of this signal transfers the content of the serial
shift register to the DAC input register.
the host controller that is selected to communicate with the DAC8871EVM. Either signal can be chosen to
drive the DAC8871 Chip Select (CS) pin. The basic function of the CS and FS signal is to drive the CS pin
of the DAC8871 to enable the device communication port and to synchronize the data going into the
device immediately following its high-to-low transition. This signal must be held low while the host
processor is accessing the DAC. The low-to-high transition of this signal transfers the content of the serial
shift register to the DAC input register.
The SCLK signal is the clock necessary to load the serial data input into the DAC’s serial shift register.
The serial clock rate can operate at speeds up to 50 MHz. The 16-bit data is shifted out of the bus master
synchronously on the falling edge of SCLK and latched on the rising edge of SCLK into the DAC’s serial
shift register. The most-significant bit (MSB) is the first bit that is sent out to the DAC. After 16-bits are
transferred or 16 SCLK cycles are generated, the bus master must take the CS signal high immediately. If
the CS signal is held low and more than 16 SCLK cycles are applied, the last SCLK cycle is considered
the location of the least-significant bit (LSB) of the 16-bit word that is loaded into the DAC’s serial shift
register. Hence, the user must know the data word alignment with respect to SCLK or the data input will
be corrupted. If this happens, simply reload the DAC latch with the new 16-bit word.
The serial clock rate can operate at speeds up to 50 MHz. The 16-bit data is shifted out of the bus master
synchronously on the falling edge of SCLK and latched on the rising edge of SCLK into the DAC’s serial
shift register. The most-significant bit (MSB) is the first bit that is sent out to the DAC. After 16-bits are
transferred or 16 SCLK cycles are generated, the bus master must take the CS signal high immediately. If
the CS signal is held low and more than 16 SCLK cycles are applied, the last SCLK cycle is considered
the location of the least-significant bit (LSB) of the 16-bit word that is loaded into the DAC’s serial shift
register. Hence, the user must know the data word alignment with respect to SCLK or the data input will
be corrupted. If this happens, simply reload the DAC latch with the new 16-bit word.
The SDI signal is the serial data input that is loaded into the DAC’s serial shift register with respect to
SCLK.
SCLK.
The LDAC signal is the control input signal necessary to load the DAC register with the content of the
input register. This signal is active low and can be triggered synchronously or asynchronously.
input register. This signal is active low and can be triggered synchronously or asynchronously.
SLAU233 – September 2007
DAC8871 Evaluation Module
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