Texas Instruments DAC8871EVM - DAC8871EVM Evaluation Module DAC8871EVM DAC8871EVM 데이터 시트
제품 코드
DAC8871EVM
www.ti.com
3.3.5
RST Signal
3.4
Analog Output
3.5
Jumper Setting
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
EVM Operation
The RST signal is the control input necessary to reset the device to a known state that is determined by
the state of the RSTSEL pin when the RST pin is asserted. If RSTSEL is tied to DGND, the DAC latch is
cleared (0 V) and V
the state of the RSTSEL pin when the RST pin is asserted. If RSTSEL is tied to DGND, the DAC latch is
cleared (0 V) and V
OUT
is minimum scale (i.e., V
REF
L). If RSTSEL is tied to V
DD
, the DAC latch is set to
midscale and V
OUT
is equal to (V
REF
H – V
REF
L)/2. This pin is active low.
The EVM includes an external operational amplifier, U2, as the output buffer circuit for the DAC. The
buffered output can be monitored through J1 pin 2, whereas the unbuffered output of the DAC can be
monitored through J1 pin 6 if R13 is populated.
buffered output can be monitored through J1 pin 2, whereas the unbuffered output of the DAC can be
monitored through J1 pin 6 if R13 is populated.
A low-pass filter circuit using R1 and C1 is also included for the DAC output, if desired. The components
are not populated by default when it ships out of the factory; therefore, the user must provide the desired
components. The resistor R1 is shunted using a jumper resistor.
are not populated by default when it ships out of the factory; therefore, the user must provide the desired
components. The resistor R1 is shunted using a jumper resistor.
shows the function of each specific jumper setting of the EVM.
Table 4. Jumper Setting Function
Jumper
Reference
Function
Setting
Routes the onboard negative voltage reference, V
REF
L for the DAC.
Disconnect onboard or external negative voltage reference, V
REF
L for the DAC via U4 or U5B or J1
W1
pin 18. Allows user reference voltage to connect via TP2.
Routes the external negative voltage reference, V
REF
L for the DAC via J1 pin 18.
Tie RSTSEL to V
DD
. DAC resets to midscale.
W2
Tie RSTSEL to DGND. DAC resets to minimum scale.
Routes the onboard positive voltage reference, V
REF
H for the DAC.
Disconnect onboard or external positive voltage reference, V
REF
H for the DAC via U5A or J1 pin
W3
20. Allows user reference voltage to connect via TP1.
Routes the external positive voltage reference, V
REF
H for the DAC via J1 pin 20.
Tie RST to V
DD
. DAC reset pin is pulled high.
W4
Tie RST to DGND. DAC is in permanent reset mode.
FS signal from J2-7 is routed to drive the CS signal of the DAC8871.
W5
CS signal from J2-1 is routed to drive the CS signal of the DAC8871.
12
DAC8871 Evaluation Module
SLAU233 – September 2007