Texas Instruments Clock Jitter Cleaner With Cascaded PLLs and Integrated 1.6 GHz VCO (LVPECL LVCMOS Outputs) LMK04002BEV LMK04002BEVAL/NOPB 데이터 시트
제품 코드
LMK04002BEVAL/NOPB
November 2013
LMK040xx Evaluation Board User’s Guide
SNAU045A
11
Copyright © 2013, Texas Instruments Incorporated
www.ti.com
LMK040xx Board Information
The LMK040xxB Evaluation Board simplifies evaluation of the LMK040xxB Precision Clock Conditioner with Dual PLLs
and Integrated VCO. See
Appendix H for interfacing the board.
The CodeLoader software will run on a Windows 7 or Windows XP PC. The CodeLoader software is used to program the
internal registers of the LMK040xxB device through a LPT or USB2ANY-uWire interface.
The following block diagram illustrates the functional architecture of the LMK040xxB clock conditioner. It features a
cascaded, dual PLL arrangement, available internal loop filter components for PLL2, internal VCO with PLL2 for frequency
synthesis, and clock distribution section with individual channel dividers and delay adjustment blocks. The dual reference
clock input to PLL1 provides fail-safe redundancy for phase locked loop operation. The cascaded PLL architecture allows
PLL1 to be used as a jitter cleaner for an incoming reference clock that contains excessive phase noise. This requires the
user to select an external oscillator (VCXO or crystal) that provides the desired phase noise performance at the output of
the clock channels. This external oscillator becomes the reference clock for PLL2 and along with the phase noise
characteristics of PLL2 and the internal VCO, determines the final phase noise performance at F
OUT
and the output of the
clock distribution section.
Figure 2. Functional Block Diagram of the LMK040xxB Dual PLL Precision Clock Conditioner with External
VCXO module.
PLL1 has been designed to work with either an off-the-shelf VCXO package or with a user -designed discrete
implementation that employs a crystal resonator and associated tuning components. The following block diagram shows
an example of a discretely implemented VCXO using a crystal resonator.
PLL2
PLL1
R
1
Dq
1
N
1
R
2
N
2
Dq
2
VCO
CLKin0
CLKin1
VCO
DIV
CHAN
DIV
D
CHAN
DIV
D
5 Output Clock
Channels
LVPECL, LVDS,
LVCMOS
F
OUT
CLKout_0
CLKout_4
uWire
Interface
DATA
CLK
LE
vcxo